Integrated circuit with delay selecting input selection circuitry

• US 7,652,498 B2
• Filed: 06/27/2007
• Issued: 01/26/2010
• Est. Priority Date: 06/27/2007
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Hutchings, Brad, Redgrave, Jason
• Primary Examiner(s): Le, Don P
• Application Number:
  US11/769,701
• Publication Number:
  US 20090002045A1
• Time in Patent Office: 944 Days
• Field of Search: 326 37- 41
• US Class Current: 326/38
• CPC Class Codes: H03K 19/177 arranged in matrix form

Abstract

Some embodiments provide an integrated circuit (IC) with a delay select input selection circuit. The delay select input selection circuit comprises a first input selection circuit, a first storage element, a second storage element, and a first input line branching into multiple input lines. The multiple input lines include at least a second, third, and fourth input line. The second input line is communicably connected to a first input of the first input selection circuit. The third input line enters the first storage element. The fourth input line enters the second storage element. An output from the first storage element is communicably connected to a second input of the first input selection circuit. An output from the second storage element is communicably connected to a third input of the first input selection circuit.

Claims

1. An integrated circuit (IC) comprising a delay select input selection circuit, said delay select input selection circuit comprising:

a) a first input selection circuit;

b) a first storage element;

c) a second storage element;

d) a first input line branching into a plurality of input lines comprising at least a second, third, and fourth input line, wherein;

i) said second input line is communicably connected to a first input of said first input selection circuit;

ii) said third input line enters said first storage element;

iii) said fourth input line enters said second storage element;

iv) an output from said first storage element is communicably connected to a second input of said first input selection circuit; and

v) an output from said second storage element is communicably connected to a third input of said first input selection circuit; and

e) a fifth input line for communicably connecting a fourth input of said first input selection circuit to an output of a second input selection circuit of another delay select input selection circuit, wherein said fifth input line is not connected to a branch of said first input line.

2. The IC of claim 1, wherein an output of said first input selection circuit is communicably connected to an input of a third input selection circuit of a third delay select input selection circuit.

3. The IC of claim 1, wherein the IC is a configurable IC.

4. The IC of claim 1, wherein the IC is a reconfigurable IC.

5. The IC of claim 1, wherein the IC is a subcycle reconfigurable IC.

6. The IC of claim 1, wherein said first storage element comprises a latch.

7. The IC of claim 2, wherein said fifth input line is not communicably connected to said first input line.

8. An integrated circuit (IC) comprising a chain of delay select input selection circuits, each delay select input selection circuit of said chain of delay select input selection circuits comprising:

a) a first input selection circuit;

b) a first storage element; and

c) a first input line for receiving data from outside the chain of delay select input selection circuits, wherein the first input line branches into a plurality of input lines comprising at least a second input line and a third input line, wherein;

i) said second input line is communicably connected to a first input of said first input selection circuit;

ii) said third input line enters said first storage element; and

iii) an output from said first storage element is communicably connected to a second input of said first input selection circuit,

wherein at least two delay select input selection circuits are communicably connected to form said chain of delay select input selection circuits.

9. The IC of claim 8, wherein an output from each of a plurality of first input selection circuits of a plurality of said delay select input selection circuits of said chain of delay select input selection circuits communicably connects to a third input of a next input selection circuit in a next delay select input selection circuit in said chain of delay select input selection circuits.

10. The IC of claim 9, wherein each of the plurality of the said delay select input selection circuits comprises a second storage element, wherein:

a) a fourth input line enters said second storage element; and

b) an output from said second storage element is communicably connected to a fourth input of said input selection circuit.

11. The IC of claim 9 further comprising a plurality of chains of delay select input selection circuits.

12. The IC of claim 9 further comprising a plurality of additional data lines branching from said outputs.

13. The IC of claim 12, wherein subsets of said plurality of additional data lines connect to input selection circuits.

14. The IC of claim 8, wherein the IC is a configurable IC.

15. The IC of claim 8, wherein the IC is a reconfigurable IC.

16. The IC of claim 8, wherein the IC is a subcycle reconfigurable IC.

17. A delay select input selection circuit comprising:

a) an input selection circuit; and

b) a first input line wherein the first input line branches into a plurality of input lines comprising at least a second input line and a third input line, wherein;

i) said second input line is communicably connected to a first input of said input selection circuit;

ii) said third input line enters a delaying circuit; and

iii) an output from said delaying circuit is communicably connected to a second input of said input selection circuit,

wherein the input selection circuit comprises at least one input that is communicably connected to an output of another delay select input selection circuit, wherein said output of another delay select input selection circuit is not connected to a branch of said first input line.

18. The delay select input selection circuit of claim 17, wherein the delaying circuit is a latch.