Embedding memory within tile arrangement of an integrated circuit

• US 7,652,499 B2
• Filed: 10/28/2007
• Issued: 01/26/2010
• Est. Priority Date: 11/08/2004
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Redgrave, Jason, Schmit, Herman
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US11/926,092
• Publication Number:
  US 20080116931A1
• Time in Patent Office: 821 Days
• Field of Search: 326 38- 41
• US Class Current: 326/38
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H03K 19/17728 Reconfigurable logic blocks, e.g. lookup tables
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/1776 for memories

Abstract

Some embodiments of the invention provide a configurable IC that includes several configurable computational tiles and several memory tiles. Each computational tile has a set of configurable logic circuits for configurably performing a plurality of computations and a set of configurable routing circuits. The routing circuits of the tiles configurably route signals between configurable logic circuits. Each memory tiles includes a set of routing circuits and a memory array for storing data on which the logic circuit perform computation. In this IC, at least a first memory tile has the same set of configurable routing circuits as at least a second computational tile.

Claims

1. An integrated circuit (IC) comprising:

a) a plurality of memory tiles each comprising a set of memory circuits and a first plurality of input select interconnects for receiving signals on a plurality of inputs and supplying the signals received on a selected set of the inputs to the memory circuits;

b) a plurality of configurable computational tiles each comprising at least one configurable logic circuit and a second plurality of input select interconnects for receiving signals on a plurality of inputs and supplying the signals received on a selected set of the inputs to the configurable logic circuit; and

c) a configurable routing fabric for passing data between said computational tiles and said memory tiles, the configurable routing fabric comprising;

a first set of configurable routing elements located in a particular arrangement within each of the plurality of memory tiles, wherein said first set of configurable routing elements comprises a first set of outputs that provides data to said first plurality of input select interconnects; and

a second set of configurable routing elements, matching said first set of configurable routing elements, located in the same particular arrangement within each of the plurality of configurable computational tiles, wherein said second set of configurable routing elements comprises a second set of outputs that provides data to said second plurality of input select interconnects.

2. The IC of claim 1, wherein the first plurality of input select interconnects are in locations on the memory tiles that correspond to the locations of the second plurality of input select interconnects on the configurable computational tiles.

3. The IC of claim 2, wherein the first and second pluralities of input select interconnects include the same number of input select interconnects in each plurality and each input select interconnect of said first plurality has the same number of inputs as a corresponding input select interconnect of said second plurality.

4. The IC of claim 3, wherein a first particular input select interconnect of the first plurality corresponds to a second particular input select interconnect of the second plurality when the relative position within a memory tile of the first particular input select interconnect is the same as the relative position within a configurable computational tile of the second particular input select interconnect.

5. The IC of claim 1, wherein said second set of configurable routing elements of a configurable computational tile are directly connected to input select interconnects of said second plurality of input select interconnects of the configurable computational tile.

6. The IC of claim 1, wherein said second set of configurable routing elements of a first configurable computational tile are directly connected to input select interconnects of said second plurality of input select interconnects of a second configurable computational tile.

7. The IC of claim 1, wherein said second set of configurable routing elements of a configurable computational tile are directly connected to input select interconnects of said first plurality of input select interconnects of a memory tile.

8. The IC of claim 1, wherein said first set of configurable routing elements of a memory tile are directly connected to input select interconnects of said second plurality of input select interconnects of a configurable computational tile.

9. The IC of claim 1, wherein said first set of configurable routing elements of a memory tile are directly connected to input select interconnects of said first plurality of input select interconnects of said memory tile.

10. The IC of claim 1, wherein said first set of configurable routing elements of a first memory tile are directly connected to input select interconnects of said first plurality of input select interconnects of a second memory tile.

11. An integrated circuit (IC) comprising:

a) a plurality of memory tiles each comprising at least one memory circuit;

b)a plurality of configurable computational tiles each comprising at least one configurable logic circuit; and

c) a configurable routing fabric comprising;

a first set of configurable routing elements located in a particular arrangement within each of the plurality of memory tiles,

a second set of configurable routing elements, matching said first set of configurable routing elements, located in the same particular arrangement within each of the plurality of configurable computational tiles, wherein said configurable routing fabric forms a configurable routing network for routing signals between configurable logic circuits and between configurable logic circuits and memory arrays, wherein the memory arrays do not create a discontinuity in the configurable routing fabric.

12. An integrated circuit (IC) comprising:

a) a plurality of memory tiles each comprising at least one memory circuit;

b) a plurality of configurable computational tiles each comprising at least one configurable logic circuit; and

c) a configurable routing fabric comprising;

a first set of configurable routing elements located in a particular arrangement within each of the plurality of memory tiles,

a second set of configurable routing elements, matching said first set of configurable routing elements, located in the same particular arrangement within each of the plurality of configurable computational tiles, wherein the configurable routing fabric in a section of the IC that contains a memory array embedded in a memory tile is the same as the configurable routing fabric in a section of the IC that contains logic circuits in a configurable computational tile.

13. An electronic device comprising an integrated circuit (IC) comprising:

a configurable routing fabric for routing signals among circuits of said IC, said configurable routing fabric comprising circuit elements distributed on a plurality of configurable computational tiles and a plurality of memory tiles, wherein each configurable computational tile comprises a set of configurable logic circuits for configurably performing a plurality of computations, each memory tile comprises at least one memory array for storing data that serve as variables in the computations of the configurable logic circuits, the circuit elements of said configurable routing fabric on a first memory tile correspond to the circuit elements of said configurable routing fabric on a second configurable computational tile wherein the circuit elements on the first tile correspond to the circuit elements on the second tile when each of the circuit elements on the first tile is the same type of circuit element as the corresponding circuit element of the second tile.

14. The electronic device of claim 13, wherein corresponding circuit elements on each of the first memory tile and the second configurable computational tile are in the same relative position on each of the first memory tile and the second configurable computational tile.

15. The electronic device of claim 13, wherein corresponding circuit elements on each of two particular configurable computational tiles are in the same relative position on each of the two particular configurable computational tiles.

16. The electronic device of claim 13, wherein the configurable routing fabric comprises identical outputs on the first memory tile and the second configurable computational tile.

17. The electronic device of claim 13, wherein a memory array of the first memory tile occupies the same position relative to the first memory tile as a set of logic circuits of the second configurable computational tile occupies relative to the second configurable computational tile.

18. The electronic device of claim 17, wherein said memory array comprises a set of inputs, said set of logic circuits comprises a set of inputs that occupies the same position relative to the second configurable computational tile as the set of inputs of the first memory tile occupies relative to the first memory tile.