Circuits and methods for detecting and assisting wire transitions

• US 7,652,507 B1
• Filed: 06/22/2006
• Issued: 01/26/2010
• Est. Priority Date: 06/08/2004
• Status: Active Grant

• Current Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Original Assignee: Intellectual Ventures Funding LLC (Intellectual Ventures LLC)
• Inventors: Kowalczyk, Andre, Masleid, Robert Paul
• Primary Examiner(s): Chang; Daniel D
• Application Number:
  US11/473,608
• Time in Patent Office: 1,314 Days
• Field of Search: 326/83, 326/86, 326/23, 326/27, 327/108, 327/112, 327/379
• US Class Current: 326/86
• CPC Class Codes: H03K 19/01721 by means of a pull-up or down element

Abstract

A circuit for assisting signal transitions on a wire, and a method thereof. The circuit includes a first subcircuit that causes a first transistor that is coupled to the circuit'"'"'s output to turn on during a rising transition and then turn off. The first transistor drives the output to a high state to assist in the rising transition. The circuit also includes a second subcircuit that causes a second transistor that is coupled to the circuit'"'"'s output to turn on during a falling transition and then turn off. The second transistor drives the output to a low state to assist in the falling transition.

Claims

1. A device comprising:

a wire for propagating a signal;

a circuit coupled to the wire, the circuit having an input and an output, the circuit causing a first transistor to turn on and then turn off, the first transistor driving the output to a first state in response to the circuit detecting a first transition in the signal, the circuit comprising a delay chain coupled between the input and the output and operable for maintaining the first state at the output with the first transistor turned off until a second transition is detected in the signal, wherein in response to the circuit detecting the second transition the circuit causes a second transistor that is coupled to the output to turn on and then turn off, the second transistor driving the output to a second state, and the circuit maintaining the second state at the output with the second transistor turned off until a third transition is detected in the signal;

the circuit further comprising first circuitry coupled to the input, the first circuitry causing the second transistor to turn on during the second transition and then turn off after a first period of time, the second transistor driving the output to the second state to assist in the second transition.

2. The device of claim 1 wherein the circuit further comprises second circuitry coupled to the input, the second circuitry causing the first transistor that is coupled to the output to turn on during the first transition and then turn off after a second period of time, the first transistor driving the output to the first state to assist in the first transition.

3. The device of claim 1 wherein the first transition is a rising transition, the first state is a high state, and the second transition is a falling transition.

4. The device of claim 1 wherein the first transition is a falling transition, the first state is a low state, and the second transition is a rising transition.

5. The device of claim 1 wherein the first circuitry comprises:

a NOR gate coupled to the wire; and

a delay chain coupled to the NOR gate.

6. The device of claim 1 wherein the first circuitry comprises:

a NAND gate coupled to the wire; and

a delay chain coupled to the NAND gate.

7. The device of claim 1 wherein the first transistor is a p-type device and the second transistor is an n-type device.

8. The device of claim 1 wherein the first transistor is an n-type device and the second transistor is a p-type device.

9. The device of claim 1 wherein the circuit comprises a plurality of gates for maintaining the first state at the output with the first transistor turned off and for maintaining the second state at the output with the second transistor turned off.

10. The device of claim 1 wherein the input is connected to the output and wherein the input and output are coupled to the wire in a lookaside configuration.

11. The device of claim 1 wherein the input and the output are coupled to the wire in a feed-through configuration.

12. A circuit for assisting signal transitions on a wire, the circuit comprising:

first circuitry coupled to the wire, wherein the first circuitry causes a first transistor to turn on in response to a rising transition of a signal on the wire and then turn off after a first period of time, wherein the first transistor drives an output of the circuit to a high state to assist in the rising transition;

second circuitry coupled to the wire, wherein the second circuitry causes a second transistor to turn on in response to a falling transition of a signal on the wire and then turn off after a second period of time, wherein the second transistor drives the output to a low state to assist in the falling transition; and

third circuitry coupled to the wire and comprising a delay chain, wherein the third circuitry maintains the high state at the output from the rising transition until the falling transition after the first transistor turns off, wherein the third circuitry also maintains the low state from the falling transition until a next rising transition after the second transistor turns off, and wherein the delay chain resets the second circuitry between the rising transition and the falling transition and also resets the first circuitry between the falling transition and the next rising transition.

13. The circuit of claim 12 wherein an input of the circuit is connected to the output and wherein the input and output are coupled to the wire in a lookaside configuration.

14. The circuit of claim 12 wherein an input of the input of the circuit and the output are coupled to the wire in a feed-through configuration.

15. The circuit of claim 12 wherein the first circuitry comprises:

a NAND gate coupled to the wire; and

a delay chain coupled to the NAND gate.

16. The circuit of claim 12 wherein the first transistor is a p-type device.

17. The circuit of claim 12 wherein the second circuitry comprises:

a NOR gate coupled to the wire; and

a delay chain coupled to the NOR gate.

18. The circuit of claim 12 wherein the second transistor is an n-type device.

19. A circuit for assisting signal transitions on a wire, the circuit comprising:

first circuitry coupled to an input and an output on the wire, wherein the first circuitry causes a first transistor to turn on in response to a rising transition of a signal on the wire and then turn off after a first period of time, wherein the first transistor drives the output of the circuit to a high state to assist in the rising transition;

second circuitry coupled to the input and to the output, wherein the second circuitry causes a second transistor to turn on in response to a falling transition of a signal on the wire and then turn off after a second period of time, wherein the second transistor drives the output to a low state to assist in the falling transition; and

third circuitry coupled between the input and the output, wherein the third circuitry maintains the high state at the output from the rising transition until the falling transition after the first transistor turns off, wherein the third circuitry also maintains the low state from the falling transition until a next rising transition after the second transistor turns off, and wherein further the third circuitry resets the first circuitry in response to the rising transition and resets the second circuitry in response to the falling transition.

20. The circuit of claim 19 wherein the input is connected to the output and wherein the input and output are coupled to the wire in a lookaside configuration.

21. The circuit of claim 19 wherein the input and the output are coupled to the wire in a feed-through configuration.

22. The circuit of claim 19 wherein the first circuitry comprises:

a NAND gate coupled to the wire; and

a delay chain coupled to the NAND gate.

23. The circuit of claim 19 wherein the first transistor is a p-type device.

24. The circuit of claim 19 wherein the second circuitry comprises:

a NOR gate coupled to the wire; and

a delay chain coupled to the NOR gate.

25. The circuit of claim 19 wherein the second transistor is an n- type device.