Clock synchronizing circuit
First Claim
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1. A clock synchronizing circuit, applied in a synchronous mirror delay (SMD) block for receiving an input clock, the clock synchronizing circuit comprising:
- a plurality of stages of clock synchronizing units, each of the clock synchronizing units used for outputting an output clock according to the input clock and an output clock of a next stage of clock synchronizing unit, each clock synchronizing unit comprising;
a forward delay unit, for outputting a first delayed clock;
a mirror control unit, coupled to the forward delay unit, for outputting a mirror clock according to the input clock and the first delayed clock, the mirror control unit comprising;
a first mirror-control device, for outputting a first mirror-controlled clock according to the input clock;
a second mirror-control device, for outputting a second mirror-controlled clock according to the first delayed clock; and
a third mirror-control device, coupled to the first mirror-control device and the second mirror-control device for outputting the mirror clock according to the input clock, the first mirror-controlled clock and the second mirror-controlled clock; and
a backward delay unit, coupled to the mirror control unit for delaying the mirror clock to the corresponding output clock;
wherein in a first timing period when the input clock has a first level and the first delayed clock has a second level, the first mirror-controlled clock has the second level, the second mirror-controlled clock has the first level and the mirror clock has the second level.
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Abstract
A clock synchronizing circuit applied in a SMD block is provided. The clock synchronizing circuit includes a number of stages of clock synchronizing units. The clock synchronizing circuit can achieve the purpose of clock synchronizing by using a novel circuit design of the forward delay unit, the mirror control unit or the backward delay unit in each stage of clock synchronizing unit or by using a short-pulse generation circuit to generate a short pulse for triggering out an output clock of each stage of forward delay unit.
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Citations
25 Claims
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1. A clock synchronizing circuit, applied in a synchronous mirror delay (SMD) block for receiving an input clock, the clock synchronizing circuit comprising:
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a plurality of stages of clock synchronizing units, each of the clock synchronizing units used for outputting an output clock according to the input clock and an output clock of a next stage of clock synchronizing unit, each clock synchronizing unit comprising; a forward delay unit, for outputting a first delayed clock; a mirror control unit, coupled to the forward delay unit, for outputting a mirror clock according to the input clock and the first delayed clock, the mirror control unit comprising; a first mirror-control device, for outputting a first mirror-controlled clock according to the input clock; a second mirror-control device, for outputting a second mirror-controlled clock according to the first delayed clock; and a third mirror-control device, coupled to the first mirror-control device and the second mirror-control device for outputting the mirror clock according to the input clock, the first mirror-controlled clock and the second mirror-controlled clock; and a backward delay unit, coupled to the mirror control unit for delaying the mirror clock to the corresponding output clock; wherein in a first timing period when the input clock has a first level and the first delayed clock has a second level, the first mirror-controlled clock has the second level, the second mirror-controlled clock has the first level and the mirror clock has the second level. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A clock synchronizing circuit, applied in a SMD block for receiving an input clock, the clock synchronizing circuit comprising:
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a plurality of stages of clock synchronizing units, each of the clock synchronizing units used for outputting an output clock according to the input clock and an output clock of a next stage of clock synchronizing unit, each clock synchronizing unit comprising; a forward delay unit, for outputting a first delayed clock according to a forward clock, wherein the forward clock in any of the stages of synchronizing units other than a first stage is the first delayed clock of a previous stage of forward delay unit, the forward delay unit comprising; a first forward-delay device, for delaying the forward clock to a forward-delayed clock by a first delay time; and a second forward-delay device, coupled to the first forward-delay device for delaying the forward-delayed clock to the first delayed clock by a second delay time; a mirror control unit, coupled to the second forward-delay device for outputting a mirror clock according to the input clock and the first delayed clock; and a backward delay unit, coupled to the mirror control unit for outputting the corresponding output clock according to the mirror clock, the backward delay unit comprising; a first backward-delay device, for delaying the mirror clock to a backward-delayed clock by a third delay time, wherein the third delay time is substantially equal to the second delay time; and a second backward-delay device, coupled to the first backward-delay device for delaying the backward-delayed clock to the corresponding output clock by a fourth delay time, wherein the fourth delay time is substantially equal to the first delay time, and the second backward-delay device has an input terminal coupled to an operational voltage. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A clock synchronizing circuit, applied in a SMD block which receives an input clock, the clock synchronizing circuit comprising:
a plurality of clock synchronizing units, each of the clock synchronizing units used for outputting an output clock according to the input clock and an output clock of a next stage of clock synchronizing unit, each clock synchronizing unit comprising; a forward delay unit for outputting a first delayed clock according to a forward clock, wherein the forward clock in any of the stages of synchronizing units other than a first stage is the first delayed clock of a previous stage of forward delay unit, the forward delay unit comprising; a forward-delay device, for delaying the forward clock to a forward-delayed clock; and a first NAND2 gate, coupled to the forward-delay device for outputting the first delayed clock according to the forward-delayed clock; a mirror control unit, coupled to the first NAND2 gate for outputting a mirror clock according to the input clock and the first delayed clock; and a backward delay unit, coupled to the mirror control unit for outputting the corresponding output clock according to the mirror clock, the backward delay unit comprising; a first backward-delay device, for delaying the mirror clock to a backward-delayed clock; a second backward-delay device, for delaying a phase of a backward clock to generate a stop signal, wherein the backward clock in any of the stages of synchronizing units other than the first stage is the mirror clock of a previous stage of mirror control unit; and a second NAND2 gate, coupled to the first backward-delay device for outputting the corresponding output clock according to the backward-delayed clock and the stop signal. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A clock synchronizing circuit, applied in a SMD block for receiving an input clock, the clock synchronizing circuit comprising:
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a short-pulse generation circuit, for outputting a short-pulse clock according to the input clock, wherein the pulse-width of the short-pulse clock is much smaller than the pulse-width of the input clock; a plurality of stages of clock synchronizing units, each of the clock synchronizing units used for outputting an output clock according to the input clock and an output clock of a next stage of clock synchronizing unit, a first stage of clock synchronizing unit receiving the short-pulse clock, each clock synchronizing unit comprising; a forward delay unit, for outputting a first delayed clock; a mirror control unit, coupled to the forward delay unit, for outputting a mirror clock according to the input clock and the first delayed clock; and a backward delay unit, coupled to the mirror control unit for delaying the mirror clock to the corresponding output clock. - View Dependent Claims (20, 21, 22, 23, 24, 25)
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Specification