Clock synchronizing circuit

• US 7,652,512 B2
• Filed: 02/07/2008
• Issued: 01/26/2010
• Est. Priority Date: 02/07/2008
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Hung, Chun-Hsiung, Ho, Wen-Chiao, Chang, Kuen-Long, Chang, Chin-Hung
• Primary Examiner(s): COX, CASSANDRA F
• Application Number:
  US12/027,285
• Publication Number:
  US 20090201060A1
• Time in Patent Office: 719 Days
• Field of Search: None
• US Class Current: 327/161
• CPC Class Codes: H03K 2005/00195 using FET's
• CPC Class Codes: H03K 5/06 by the use of delay lines or other analogue delay elements
• CPC Class Codes: H03K 5/135 by the use of time reference signals, e.g. clock signals

Abstract

A clock synchronizing circuit applied in a SMD block is provided. The clock synchronizing circuit includes a number of stages of clock synchronizing units. The clock synchronizing circuit can achieve the purpose of clock synchronizing by using a novel circuit design of the forward delay unit, the mirror control unit or the backward delay unit in each stage of clock synchronizing unit or by using a short-pulse generation circuit to generate a short pulse for triggering out an output clock of each stage of forward delay unit.

Claims

1. A clock synchronizing circuit, applied in a synchronous mirror delay (SMD) block for receiving an input clock, the clock synchronizing circuit comprising:

a plurality of stages of clock synchronizing units, each of the clock synchronizing units used for outputting an output clock according to the input clock and an output clock of a next stage of clock synchronizing unit, each clock synchronizing unit comprising;

a forward delay unit, for outputting a first delayed clock;

a mirror control unit, coupled to the forward delay unit, for outputting a mirror clock according to the input clock and the first delayed clock, the mirror control unit comprising;

a first mirror-control device, for outputting a first mirror-controlled clock according to the input clock;

a second mirror-control device, for outputting a second mirror-controlled clock according to the first delayed clock; and

a third mirror-control device, coupled to the first mirror-control device and the second mirror-control device for outputting the mirror clock according to the input clock, the first mirror-controlled clock and the second mirror-controlled clock; and

a backward delay unit, coupled to the mirror control unit for delaying the mirror clock to the corresponding output clock;

wherein in a first timing period when the input clock has a first level and the first delayed clock has a second level, the first mirror-controlled clock has the second level, the second mirror-controlled clock has the first level and the mirror clock has the second level.

2. The clock synchronizing circuit according to claim 1, wherein in a second timing period when both of the input clock and the first delayed clock have the second level, all of the first mirror-controlled clock, the second mirror-controlled clock and the mirror clock have the first level;

in a third timing period when the input clock has the second level and the first delayed clock has the first level, the first mirror-controlled clock has the first level, the second mirror-controlled clock has the second level and the mirror clock has the first level;

in a fourth timing period when both of the input clock and the first delayed clock have the first level, all of the first mirror-controlled clock, the second mirror-controlled clock and the mirror clock have the second level.

3. The clock synchronizing circuit according to claim 1, wherein in a first previous timing period when the input clock has the second level and the first delayed clock has the first level, the mirror clock has the second level, in a second previous timing period when the input clock has the second level and the first delayed clock has the second level, the mirror clock has the second level, and in a third previous timing period when the input clock has the first level and the first delayed clock has the second level, the mirror clock has the second level.

4. The clock synchronizing circuit according to claim 1, wherein the first mirror-control device comprises a first inverter for outputting the first mirror-controlled clock according to the input clock.

5. The clock synchronizing circuit according to claim 4, wherein the second mirror-control device comprises a second inverter coupled to the first inverter in series for outputting the mirror-controlled clock according to the first delayed clock.

6. The clock synchronizing circuit according to claim 5, wherein the third mirror-control device comprises:

a first metal oxide semiconductor (MOS) transistor comprising a gate receiving the second mirror-controlled clock and a source receiving the first mirror-controlled clock;

a second MOS transistor comprising a gate connected to the gate of the first MOS transistor and a source grounded;

a third MOS transistor comprising a source connected to a drain of the first MOS transistor and a drain connected to a drain of the second MOS transistor;

a fourth MOS transistor comprising a gate connected to a gate of the third MOS transistor for receiving the input clock and a drain for outputting the mirror clock;

a fifth MOS transistor comprising a gate connected to the gate of the third MOS transistor and a drain connected to the drain of the fourth MOS transistor; and

a sixth MOS transistor comprising a gate connected to the drain of the second MOS transistor and a drain connected to a source of the fifth MOS transistor.

7. A clock synchronizing circuit, applied in a SMD block for receiving an input clock, the clock synchronizing circuit comprising:

a plurality of stages of clock synchronizing units, each of the clock synchronizing units used for outputting an output clock according to the input clock and an output clock of a next stage of clock synchronizing unit, each clock synchronizing unit comprising;

a forward delay unit, for outputting a first delayed clock according to a forward clock, wherein the forward clock in any of the stages of synchronizing units other than a first stage is the first delayed clock of a previous stage of forward delay unit, the forward delay unit comprising;

a first forward-delay device, for delaying the forward clock to a forward-delayed clock by a first delay time; and

a second forward-delay device, coupled to the first forward-delay device for delaying the forward-delayed clock to the first delayed clock by a second delay time;

a mirror control unit, coupled to the second forward-delay device for outputting a mirror clock according to the input clock and the first delayed clock; and

a backward delay unit, coupled to the mirror control unit for outputting the corresponding output clock according to the mirror clock, the backward delay unit comprising;

a first backward-delay device, for delaying the mirror clock to a backward-delayed clock by a third delay time, wherein the third delay time is substantially equal to the second delay time; and

a second backward-delay device, coupled to the first backward-delay device for delaying the backward-delayed clock to the corresponding output clock by a fourth delay time, wherein the fourth delay time is substantially equal to the first delay time, and the second backward-delay device has an input terminal coupled to an operational voltage.

8. The clock synchronizing circuit according to claim 7, wherein the first forward-delay device is a first NAND2 gate for receiving the forward clock, the second forward-delay device is a second NAND2 gate connected to an output terminal of the first NAND2 gate and the operational voltage for outputting the first delayed clock, the first backward-delay device is a third NAND2 gate for receiving the mirror clock, and the second backward-delay device is a fourth NAND2 gate connected to an output terminal of the third NAND2 gate and the operational voltage for outputting the corresponding output clock.

9. The clock synchronizing circuit according to claim 7, wherein the first forward-delay device comprises a first NAND2 gate for receiving the forward clock, and a first inverter connected to an output terminal of the first NAND2 gate, the second forward-delay device comprises a second inverter connected to an output terminal of the first inverter and a second NAND2 gate connected to an output terminal of the second inverter and an operational voltage for outputting the first delayed clock, the first backward-delay device comprises a third NAND2 gate for receiving the mirror clock, and a third inverter connected to an output terminal of the third NAND2 gate, the second backward-delay device comprises a fourth inverter connected to an output terminal of the third converter and a fourth NAND2 gate connected to an output terminal of the fourth inverter and the operational voltage for outputting the corresponding output clock.

10. The clock synchronizing circuit according to claim 7, wherein the mirror control circuit comprises an NAND2 gate for outputting the mirror clock according to the input clock and the first delayed clock.

11. The clock synchronizing circuit according to claim 7, wherein the mirror control circuit comprises:

a first inverter, for outputting a first phase-inverted clock according to the input clock;

a second inverter, for outputting a second phase-inverted clock according to the first delayed clock;

a first MOS transistor comprising a gate receiving the second phase-inverted clock and a source receiving the first phase-inverted clock;

a second MOS transistor comprising a gate connected to the gate of the first MOS transistor and a source grounded;

a third MOS transistor comprising a source connected to a drain of the first MOS transistor and a drain connected to a drain of the second MOS transistor;

a fourth MOS transistor comprising a gate connected to a gate of the third MOS transistor and a drain for outputting the mirror clock;

a fifth MOS transistor comprising a gate connected to the gate of the third MOS transistor and a drain connected to the drain of the fourth MOS transistor; and

a sixth MOS transistor comprising a gate connected to the drain of the second MOS transistor and a drain connect to a source of the fifth MOS transistor.

12. The clock synchronizing circuit according to claim 7, further comprising a short-pulse generation circuit for outputting a short-pulse clock according to the input clock, wherein the pulse-width of the short-pulse clock is much smaller than the pulse-width of the input clock.

13. A clock synchronizing circuit, applied in a SMD block which receives an input clock, the clock synchronizing circuit comprising:

a plurality of clock synchronizing units, each of the clock synchronizing units used for outputting an output clock according to the input clock and an output clock of a next stage of clock synchronizing unit, each clock synchronizing unit comprising;

a forward delay unit for outputting a first delayed clock according to a forward clock, wherein the forward clock in any of the stages of synchronizing units other than a first stage is the first delayed clock of a previous stage of forward delay unit, the forward delay unit comprising;

a forward-delay device, for delaying the forward clock to a forward-delayed clock; and

a first NAND2 gate, coupled to the forward-delay device for outputting the first delayed clock according to the forward-delayed clock;

a mirror control unit, coupled to the first NAND2 gate for outputting a mirror clock according to the input clock and the first delayed clock; and

a backward delay unit, coupled to the mirror control unit for outputting the corresponding output clock according to the mirror clock, the backward delay unit comprising;

a first backward-delay device, for delaying the mirror clock to a backward-delayed clock;

a second backward-delay device, for delaying a phase of a backward clock to generate a stop signal, wherein the backward clock in any of the stages of synchronizing units other than the first stage is the mirror clock of a previous stage of mirror control unit; and

a second NAND2 gate, coupled to the first backward-delay device for outputting the corresponding output clock according to the backward-delayed clock and the stop signal.

14. The clock synchronizing circuit according to claim 13, wherein the second backward-delay device comprises two serial-connected inverters for outputting the stop signal according to the backward clock.

15. The clock synchronizing circuit according to claim 13, wherein the forward-delay device comprises a third NAND2 gate coupled to the first NAND2 gate in series for receiving the forward clock, and the first backward-delay device comprises a fourth NAND2 gate coupled to the second NAND2 gate in series for receiving the mirror clock.

16. The clock synchronizing circuit according to claim 13, wherein the forward-delay device comprises a third NAND2 gate for receiving the forward clock, a first inverter connected to an output terminal of the third NAND2 gate, a second inverter connected to the first inverter in series for outputting the forward-delayed clock, and the first backward-delay device comprises a fourth NAND2 gate for receiving the mirror clock, a third inverter connected to an output terminal of the fourth NAND2 gate and a fourth inverter connected to the third inverter in series for outputting the backward-delayed clock.

17. The clock synchronizing circuit according to claim 13, wherein the mirror control circuit comprises:

a first inverter, for outputting a first phase-inverted clock according to the input clock;

a second inverter, for outputting a second phase-inverted clock according to the first delayed clock; and

a first MOS transistor comprising a gate receiving the second phase-inverted clock and a source receiving the first phase-inverted clock;

a second MOS transistor comprising a gate connected to the gate of the first MOS transistor and a source grounded;

a third MOS transistor comprising a source connected to a drain of the first MOS transistor and a drain connected to a drain of the second MOS transistor;

a fourth MOS transistor comprising a gate connected to a gate of the third MOS transistor and a drain for outputting the mirror clock;

a fifth MOS transistor comprising a gate connected to the gate of the third MOS transistor and a drain connected to the drain of the fourth MOS transistor; and

a sixth MOS transistor comprising a gate connected to the drain of the second MOS transistor and a drain connect to a source of the fifth MOS transistor.

18. The clock synchronizing circuit according to claim 13, further comprising a short-pulse generation circuit for outputting a short-pulse clock according to the input clock, wherein the pulse-width of the short-pulse clock is much smaller than the pulse-width of the input clock.

19. A clock synchronizing circuit, applied in a SMD block for receiving an input clock, the clock synchronizing circuit comprising:

a short-pulse generation circuit, for outputting a short-pulse clock according to the input clock, wherein the pulse-width of the short-pulse clock is much smaller than the pulse-width of the input clock;

a plurality of stages of clock synchronizing units, each of the clock synchronizing units used for outputting an output clock according to the input clock and an output clock of a next stage of clock synchronizing unit, a first stage of clock synchronizing unit receiving the short-pulse clock, each clock synchronizing unit comprising;

a forward delay unit, for outputting a first delayed clock;

a mirror control unit, coupled to the forward delay unit, for outputting a mirror clock according to the input clock and the first delayed clock; and

a backward delay unit, coupled to the mirror control unit for delaying the mirror clock to the corresponding output clock.

20. The clock synchronizing circuit according to claim 19, wherein the short-pulse generation circuit comprises:

a delay monitor circuit (DMC), for outputting a delay-monitor clock according to the input clock; and

a short-pulse generator, coupled to the DMC for outputting the short-pulse clock according to the delay-monitor clock, the short-pulse generator comprising;

N inverters, coupled in series to the DMC for outputting a phase-inverted clock according to the delay-monitor clock, wherein N is an odd number, N≧

3; and

an AND gate, coupled to the DMC and the N converters for performing an AND gate operation on the delay-monitor clock and the phase-inverted clock and accordingly outputting the short-pulse clock.

21. The clock synchronizing circuit according to claim 20, wherein the short-pulse generator further comprises a RC circuit coupled between the N inverters and the AND gate.

22. The clock synchronizing circuit according to claim 20, wherein the short-pulse generator further comprises a selection circuit coupled to the N inverters for selectively outputting the phase-inverted clock according to the delay-monitor clock via M inverters of the N inverters, wherein M is an odd number and M≦

N.

23. The clock synchronizing circuit according to claim 19, wherein the short-pulse generation circuit comprises:

a short-pulse generator, for outputting an initial short-pulse clock according to the input clock, the short-pulse generator comprising;

N inverters, coupled in series for outputting a phase-inverted clock according to the input clock, wherein N is an odd number, N≧

3; and

an AND gate, coupled to the N converters for performing an AND gate operation on the input clock and the phase-inverted clock and accordingly outputting the initial short-pulse clock; and

a DMC, for delaying the initial short-pulse clock to generate the short-pulse clock.

24. The clock synchronizing circuit according to claim 23, wherein the short-pulse generator further comprises a RC circuit coupled between the N inverters and the AND gate.

25. The clock synchronizing circuit according to claim 23, wherein the short-pulse generator further comprises a selection circuit coupled to the N inverters for selectively outputting the phase-inverted clock according to the input clock via M inverters of the N inverters, wherein M is an odd number and M N.