Programmable analog-to-digital converter for low-power DC-DC SMPS

• US 7,652,604 B2
• Filed: 07/03/2007
• Issued: 01/26/2010
• Est. Priority Date: 02/28/2007
• Status: Active Grant

• Current Assignee: Exar Corporation (Maxlinear Incorporated)
• Original Assignee: Exar Corporation (Maxlinear Incorporated)
• Inventors: Prodic, Aleksandar, Parayandeh, Amir
• Primary Examiner(s): Mai; Lam T
• Application Number:
  US11/773,330
• Publication Number:
  US 20080204290A1
• Time in Patent Office: 938 Days
• Field of Search: 341143-155
• US Class Current: 341/143
• CPC Class Codes: H02M 3/157 with digital control
• CPC Class Codes: H03K 7/08 Duration or width modulation ; Duty cycle modulation
• CPC Class Codes: H03M 1/502 using tapped delay lines

Abstract

A voltage-to-time based windowed analog-to-digital converter (ADC) can have programmable reference voltage, conversion time, and accuracy of voltage regulation. The ADC can be fully implemented on a small silicon area and is suitable for implementation in various integrated digital controllers for high-frequency low-power switch-mode power supplies (SMPS). The programmable characteristics can be achieved through the utilization of the inherent averaging effect of the delay line or of the other voltage-to-time conversion structures and through the adjustments of delay cells'"'"' propagation times or the effective voltage-to-time conversion ratio in alternative structures.

Claims

1. A circuit comprising:

a sigma-delta DAC that receives a digital value and outputs an analog reference voltage output whose average is related to the digital value; and

a windowed ADC converter including a reference voltage-to-time converter that is adjusted using the analog reference voltage output of the sigma-delta DAC and a measurement voltage-to-time converter that is adjusted using a system output voltage wherein the windowed ADC converter determines an error value and wherein the reference and the measurement voltage-to-time converters are a moving average filter.

2. The circuit of claim 1, wherein one of the voltage-to-time converters is a delay line.

3. The circuit of claim 1, wherein one of the voltage-to-time converters is a ring oscillator whose supply voltage is changing.

4. The circuit of claim 1, wherein one of the voltage-to-time converters is a conventional voltage controlled oscillator.

5. The circuit of claim 4, wherein a frequency of voltage control oscillator is dynamically changed.

6. The circuit of claim 5, wherein a selectable frequencies of the voltage control oscillator is integer multiples.

7. The circuit of claim 1, wherein the sigma-delta DAC includes an RC filter.

8. The circuit of claim 1 wherein averaging effects of the reference and the measurement voltage-to-time converters are used to minimize a size of on-chip RC filters of sigma-delta based digital to analog converters.

9. The circuit of claim 8, wherein an RC filter corner frequency is selected to be relatively close to the moving average filter notch frequency of the windowed ADC with voltage-to-time converters with averaging effect.

10. The circuit of claim 1, wherein the error indicates a difference of the system output voltage from a digital reference value.

11. The circuit of claim 10, wherein the digital value sent to the sigma-delta DAC is a lower bit or bits of the digital reference value.

12. The circuit of claim 1, wherein the reference voltage-to-time converter is a reference delay line and the measurement voltage-to-time converter is a measurement delay line and wherein a difference in a number of delay cells in the reference delay line and measurement delay line through which a clock passes is used to determine the error.

13. The circuit of claim 12, wherein some of delay cells are programmable to have a programmable delay that is a selectable multiple of the delay of the other delay cells.

14. The circuit of claim 13, wherein the selectable delays are integer multiples.

15. The circuit of claim 14, wherein the integer multiple is selectable to be a integer from 1 to 2^k.

16. The circuit of claim 15, wherein a total delay of the reference delays line can be selectable over a range of values greater than the number of delay cells.

17. The circuit of claim 1, wherein a general voltage-to-time conversion period is dynamically changed.

18. A circuit comprising:

a sigma-delta unit; and

a second unit connected to an output of the sigma-delta unit, the second unit including a reference delay line and measurement delay line wherein an error decoder of the second unit produces an error signal that is derived from a number of delay cells that a clock signal passes through the measurement delay line in a time it takes for the clock signal to pass through a predetermined section of the reference delay line.

19. The circuit of claim 18, wherein the reference delay line is adjusted by a value related to the output of the sigma-delta unit.

20. The circuit of claim 18, wherein the reference delay line and measurement delay line include delay cells that operate at a selectable integer multiple of the delay of other delay cells.