Array substrate for LCD device having dual metal-layer gate and data lines and manufacturing method thereof
First Claim
1. An array substrate for use in a liquid crystal display device, comprising:
- a gate electrode, a gate line and a gate pad electrode on a substrate, wherein all of the gate electrode, the gate line and the gate pad electrode have a double-layered structure including a first barrier metal layer and a first copper layer, wherein the first barrier metal layer is interposed between the substrate and the first copper layer, wherein sides of the first copper layer are inside of sides of the first barrier metal layer and wherein the first barrier metal layer and the first copper layer have a smooth taper shape without any steps on their sides;
a buffer layer between the substrate and the first barrier metal layer, wherein the buffer layer is a double layer;
a gate insulation layer on the substrate covering the double-layered gate electrode, gate line and gate pad;
an active layer and an ohmic contact layer sequentially formed on the gate insulation layer and over the gate electrode;
a data line on the gate insulation layer crossing the gate line, source and drain electrodes contacting the ohmic contact layer, and a data pad electrode on the gate insulation layer, wherein all of the data line, the source and drain electrodes, and the data pad electrode have a double-layered structure including a second barrier metal layer and a second copper layer, wherein the second barrier metal layer is interposed between the substrate and the second copper layer, wherein each of the first and second barrier metal layers includes a metallic material that has a good adhesive characteristic to the substrate and prevents a reaction between the second copper layer and both the active layer and the ohmic contact layer, and wherein the metallic material is one of tantalum (Ta) and titanium (Ti);
a passivation layer formed on the gate insulation layer to cover the double-layered data line, source and drain electrodes, and data pad electrode, wherein the passivation layer has a drain contact hole exposing the drain electrode, a gate pad contact hole exposing the gate pad electrode, and a data pad contact hole exposing the data pad; and
a pixel electrode, a gate pad terminal and a data pad terminal all of which are formed of a transparent conductive material on the passivation layer.
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Abstract
The present invention is an array substrate for use in a liquid crystal display device, which includes a first double-layered metal structure and a second double-layered metal structure. The first double-layered metal structure includes a gate electrode, a gate line and a gate pad electrode on a substrate, wherein all of the gate electrode, the gate line and the gate pad electrode have a first barrier metal layer and a first copper layer. The second double-layered metal structure includes a data line, source and drain electrodes, a capacitor electrode, and a data pad electrode, wherein all of the data line, the source and drain electrodes, the capacitor electrode and the data pad electrode have a second barrier metal layer and a second copper layer.
69 Citations
21 Claims
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1. An array substrate for use in a liquid crystal display device, comprising:
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a gate electrode, a gate line and a gate pad electrode on a substrate, wherein all of the gate electrode, the gate line and the gate pad electrode have a double-layered structure including a first barrier metal layer and a first copper layer, wherein the first barrier metal layer is interposed between the substrate and the first copper layer, wherein sides of the first copper layer are inside of sides of the first barrier metal layer and wherein the first barrier metal layer and the first copper layer have a smooth taper shape without any steps on their sides; a buffer layer between the substrate and the first barrier metal layer, wherein the buffer layer is a double layer; a gate insulation layer on the substrate covering the double-layered gate electrode, gate line and gate pad; an active layer and an ohmic contact layer sequentially formed on the gate insulation layer and over the gate electrode; a data line on the gate insulation layer crossing the gate line, source and drain electrodes contacting the ohmic contact layer, and a data pad electrode on the gate insulation layer, wherein all of the data line, the source and drain electrodes, and the data pad electrode have a double-layered structure including a second barrier metal layer and a second copper layer, wherein the second barrier metal layer is interposed between the substrate and the second copper layer, wherein each of the first and second barrier metal layers includes a metallic material that has a good adhesive characteristic to the substrate and prevents a reaction between the second copper layer and both the active layer and the ohmic contact layer, and wherein the metallic material is one of tantalum (Ta) and titanium (Ti); a passivation layer formed on the gate insulation layer to cover the double-layered data line, source and drain electrodes, and data pad electrode, wherein the passivation layer has a drain contact hole exposing the drain electrode, a gate pad contact hole exposing the gate pad electrode, and a data pad contact hole exposing the data pad; and a pixel electrode, a gate pad terminal and a data pad terminal all of which are formed of a transparent conductive material on the passivation layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method of forming an array substrate for use in a liquid crystal display device, comprising:
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forming a gate electrode, a gate line and a gate pad electrode on a substrate, wherein all of the gate electrode, the gate line and the gate pad electrode have a double-layered structure including a first barrier metal layer and a first copper layer, wherein the first barrier metal layer is interposed between the substrate and the first copper layer, wherein sides of the first copper layer are inside of sides of the first barrier metal layer, and wherein the first barrier metal layer and the first copper layer have a smooth taper shape without any steps on their sides; forming a buffer layer between the substrate and the first barrier metal layer, wherein the buffer layer is a double layer; forming a gate insulation layer on the substrate to cover the double-layered gate electrode, gate line and gate pad; forming an active layer and an ohmic contact layer sequentially on the gate insulation layer and over the gate electrode; forming a data line, source and drain electrodes and a data pad electrode, wherein the data line is on the gate insulation layer and crossed the gate line, wherein the source and drain electrodes contact the ohmic contact layer, wherein the data pad electrode is disposed on the gate insulation layer, wherein all of the data line, the source and drain electrodes, the capacitor electrode and the data pad electrode have a double-layered structure including a second barrier metal layer and a second copper layer, wherein the second barrier metal layer and the second copper layer of each of the data line, the source and drain electrodes, the capacitor electrode and the data pad electrode are simultaneously etched by a same etching solution, wherein the second barrier metal layer is interposed between the substrate and the second copper layer, wherein each of the first and second barrier metal layers includes a metallic material that has a good adhesive characteristic to the substrate and prevents a reaction between the second copper layer and both the active layer and the ohmic contact layer, and wherein the metallic material is any of tantalum (Ta) and titanium (Ti); forming a passivation layer formed on the gate insulation layer to cover the double-layered data line, source and drain electrodes, and data pad electrode, wherein the passivation layer has a drain contact hole exposing the drain electrode, a gate pad contact hole exposing the gate pad electrode, and a data pad contact hole exposing the data pad; and forming a pixel electrode, a gate pad terminal and a data pad terminal on the passivation layer using a transparent conductive material. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification