Multiple independent serial link memory

• US 7,652,922 B2
• Filed: 12/30/2005
• Issued: 01/26/2010
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Kim, Jin-Ki, Pyeon, Hong Beom
• Primary Examiner(s): Nguyen; Tan T.
• Application Number:
  US11/324,023
• Publication Number:
  US 20070076479A1
• Time in Patent Office: 1,488 Days
• Field of Search: 365/219, 365/221
• US Class Current: 365/185.11
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 2216/30 Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 8/10 Decoders

Abstract

An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.

Claims

1. A semiconductor memory device comprising:

a plurality of independently controllable memory blocks;

a plurality of data link interfaces operable to independently transfer input data or output data between any one of the plurality of data link interfaces and any one of the plurality of memory blocks, each of the plurality of data link interfaces having input buffers for receiving the input data and output drivers for driving the output data; and

,

a control module configured to control substantially simultaneous data transfer during independent memory operations, to and from at least two of the plurality of data link interfaces.

2. The semiconductor memory device of claim 1, wherein the memory blocks comprise non-volatile memory banks.

3. The semiconductor memory device of claim 2, wherein the non-volatile memory blocks are flash memory blocks.

4. The semiconductor memory device of claim 3, wherein the flash memory blocks comprise serially connected transistor memory cells.

5. The semiconductor memory device of claim 3, wherein the flash memory blocks comprise parallel connected transistor memory cells.

6. The semiconductor memory device of claim 1, wherein the control module receives computer-executable instructions to control the transfer of serial input data and serial output data to and from one of the plurality of memory blocks.

7. The semiconductor memory device of claim 6, wherein the control module controls the transfer of the serial input data in response to address information contained in an address field of the serial input data.

8. The semiconductor memory device of claim 6, wherein the plurality of memory blocks, the plurality of data link interfaces and the control module are located within a single package having a one-side pad architecture.

9. The semiconductor memory device of claim 1, wherein the plurality of data link interfaces comprises two data link interfaces.

10. The semiconductor memory device of claim 1, wherein the plurality of data link interfaces comprises four data link interfaces.

11. The semiconductor memory device of claim 1, wherein the plurality of data link interfaces receive data serially.

12. The semiconductor memory device of claim 1, wherein the plurality of data link interfaces output data serially.

13. The semiconductor memory device of claim 1, wherein each of the plurality of data link interfaces comprises an input data port and an output data port.

14. The semiconductor memory device of claim 1, wherein the plurality of memory blocks is a plurality of NAND flash memory blocks.

15. The semiconductor memory device of claim 1, wherein the plurality of data link interfaces are independently controllable to access any address in any of the plurality of memory blocks.

16. The semiconductor memory device of claim 15, wherein the plurality of data link interfaces are independently controllable to access any row in any of the plurality of memory blocks.

17. The semiconductor memory device of claim 15, wherein the plurality of data link interfaces are independently controllable to access any column in any of the plurality of memory blocks.

18. The semiconductor memory device of claim 1, wherein the plurality of data link interfaces are independently controllable to perform any operation.

19. A method of controlling the transfer of data between a serial data link interface and a plurality of memory banks in a semiconductor memory device, the method comprising:

(a) receiving a data stream at a serial data link interface;

(b) parsing the data stream to extract a first memory bank identifier;

(c) updating a first memory bank status indicator corresponding to the first memory bank to indicate that the first memory bank is being utilized; and

(d) routing data between the serial data link and the first memory bank.

20. The method of claim 19, wherein (c) comprises setting a bit value in a status register.

21. The method of claim 19, further including, after (d) updating the memory bank status indicator to indicate that the memory bank is no longer being utilized.

22. The method of claim 19, further comprising:

(e) receiving a second data stream at the serial link interfaces;

(f) parsing the second data stream to extract a second memory bank identifier;

(i) updating a memory bank status indicator corresponding to the second memory bank identifier to indicate that the second memory bank is being utilized; and

(j) during a time period that at least overlaps with a time period that (d) is performed, routing data between the serial link interface and the second memory bank.

23. The method of claim 19, wherein (d) and (j) are performed using separate processing threads.

24. The method of claim 19, further comprising:

(e) receiving from the serial link interface a request for data stored in a second memory bank;

(f) updating a memory bank status indicator corresponding to the second memory bank to indicate that the second memory bank is being utilized; and

(g) during a time period that at least overlaps with a time period that (d) is performed, routing data between the second memory bank and the serial link interface.

25. The method of claim 24, wherein (d) and (g) are performed using separate processing threads.

26. A semiconductor memory device comprising:

a plurality of independently controllable memory blocks; and

a plurality of data link interfaces operable to independently transfer data between any one of the plurality of data link interfaces and any one of the plurality of independently controllable memory blocks, the plurality of data link interfaces being operable to receive or provide the data to and from input/output pins in overlapping time periods during non-volatile memory data transfer operations, each of the plurality of data link interfaces having input buffers in electrical communication with the input pins for receiving input data and output drivers in electrical communication with the output pins for driving output data.

27. The semiconductor memory device of claim 26, wherein the non-volatile memory data transfer operations occurring during the overlapping time periods include at least one of page read, program and erase operations.

28. The semiconductor memory device of claim 26, wherein the plurality of independently controllable memory blocks comprise non-volatile memory blocks.

29. The semiconductor memory device of claim 28, wherein the non-volatile memory blocks are flash memory blocks.

30. The semiconductor memory device of claim 29, wherein the flash memory blocks comprise serially connected transistor memory cells.

31. The semiconductor memory device of claim 29, wherein the flash memory blocks comprise parallel connected transistor memory cells.

32. The semiconductor memory device of claim 26, wherein the plurality of independently controllable memory blocks and the plurality of data link interfaces are located within the chip package having a one-side pad architecture, the input/output pins coupling the data through the package to the plurality of data link interfaces.

33. The semiconductor memory device of claim 26, wherein the plurality of data link interfaces receive data serially.

34. A semiconductor memory device in a chip package comprising:

a clock input pin in the chip package for receiving a clock signal;

a plurality of independently controllable memory blocks; and

a plurality of data link interfaces each including an input data port and an output data port in the chip package, the plurality of data link interfaces being synchronized with the clock signal and operable to independently transfer data between any one of the plurality of data link interfaces and any one of the plurality of memory blocks during non-volatile memory data transfer operations, each of the plurality of data link interfaces having input buffers coupled to the input data port for receiving input data and output drivers coupled to the output data port for driving output data.

35. The semiconductor memory device of claim 34, wherein the plurality of independently controllable memory blocks comprise non-volatile memory blocks.

36. The semiconductor memory device of claim 35, wherein the non-volatile memory blocks are flash memory blocks.

37. The semiconductor memory device of claim 36, wherein the flash memory blocks comprise serially connected transistor memory cells.

38. The semiconductor memory device of claim 36, wherein the flash memory blocks comprise parallel connected transistor memory cells.

39. The semiconductor memory device of claim 34, wherein the chip package has a one-side pad architecture.

40. A semiconductor memory device in a chip package comprising:

a clock input pin in the chip package for receiving a clock signal;

a plurality of independently controllable memory blocks; and

a plurality of data link interfaces for receiving and outputting data serially, the plurality of data link interfaces synchronized with the clock signal and operable to independently transfer input data or output data between any one of the plurality of data link interfaces and any one of the plurality of memory blocks during non-volatile memory data transfer operations, each of the plurality of data link interfaces having input buffers for receiving the input data and output drivers for driving the output data.

41. The semiconductor memory device of claim 40, wherein the plurality of independently controllable memory blocks comprise non-volatile memory blocks.

42. The semiconductor memory device of claim 41, wherein the non-volatile memory blocks are flash memory blocks.

43. The semiconductor memory device of claim 42, wherein the flash memory blocks comprise serially connected transistor memory cells.

44. The semiconductor memory device of claim 42, wherein the flash memory blocks comprise parallel connected transistor memory cells.

45. The semiconductor memory device of claim 40, wherein the chip package has a one-side pad architecture.

46. A semiconductor memory device in a chip package comprising:

a clock input pin in the chip package for receiving a clock signal;

a plurality of independently controllable memory blocks; and

a plurality of data link interfaces for receiving and outputting in single-bit-wide data streams, the plurality of data link interfaces synchronized with the clock signal and operable to independently transfer input data or output data between any one of the plurality of data link interfaces and any one of the plurality of memory blocks during non-volatile memory data transfer operations, each of the plurality of data link interfaces having input buffers for receiving the input data and output drivers for driving the output data.

47. The semiconductor memory device of claim 46, wherein the plurality of independently controllable memory blocks comprise non-volatile memory blocks.

48. The semiconductor memory device of claim 47, wherein the non-volatile memory blocks are flash memory blocks.

49. The semiconductor memory device of claim 48, wherein the flash memory blocks comprise serially connected transistor memory cells.

50. The semiconductor memory device of claim 48, wherein the flash memory blocks comprise parallel connected transistor memory cells.

51. The semiconductor memory device of claim 46, wherein the chip package has a one-side pad architecture.