Multiple independent serial link memory
First Claim
Patent Images
1. A semiconductor memory device comprising:
- a plurality of independently controllable memory blocks;
a plurality of data link interfaces operable to independently transfer input data or output data between any one of the plurality of data link interfaces and any one of the plurality of memory blocks, each of the plurality of data link interfaces having input buffers for receiving the input data and output drivers for driving the output data; and
,a control module configured to control substantially simultaneous data transfer during independent memory operations, to and from at least two of the plurality of data link interfaces.
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Abstract
An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.
175 Citations
51 Claims
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1. A semiconductor memory device comprising:
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a plurality of independently controllable memory blocks; a plurality of data link interfaces operable to independently transfer input data or output data between any one of the plurality of data link interfaces and any one of the plurality of memory blocks, each of the plurality of data link interfaces having input buffers for receiving the input data and output drivers for driving the output data; and
,a control module configured to control substantially simultaneous data transfer during independent memory operations, to and from at least two of the plurality of data link interfaces. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A method of controlling the transfer of data between a serial data link interface and a plurality of memory banks in a semiconductor memory device, the method comprising:
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(a) receiving a data stream at a serial data link interface; (b) parsing the data stream to extract a first memory bank identifier; (c) updating a first memory bank status indicator corresponding to the first memory bank to indicate that the first memory bank is being utilized; and (d) routing data between the serial data link and the first memory bank. - View Dependent Claims (20, 21, 22, 23, 24, 25)
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26. A semiconductor memory device comprising:
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a plurality of independently controllable memory blocks; and a plurality of data link interfaces operable to independently transfer data between any one of the plurality of data link interfaces and any one of the plurality of independently controllable memory blocks, the plurality of data link interfaces being operable to receive or provide the data to and from input/output pins in overlapping time periods during non-volatile memory data transfer operations, each of the plurality of data link interfaces having input buffers in electrical communication with the input pins for receiving input data and output drivers in electrical communication with the output pins for driving output data. - View Dependent Claims (27, 28, 29, 30, 31, 32, 33)
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34. A semiconductor memory device in a chip package comprising:
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a clock input pin in the chip package for receiving a clock signal; a plurality of independently controllable memory blocks; and a plurality of data link interfaces each including an input data port and an output data port in the chip package, the plurality of data link interfaces being synchronized with the clock signal and operable to independently transfer data between any one of the plurality of data link interfaces and any one of the plurality of memory blocks during non-volatile memory data transfer operations, each of the plurality of data link interfaces having input buffers coupled to the input data port for receiving input data and output drivers coupled to the output data port for driving output data. - View Dependent Claims (35, 36, 37, 38, 39)
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40. A semiconductor memory device in a chip package comprising:
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a clock input pin in the chip package for receiving a clock signal; a plurality of independently controllable memory blocks; and a plurality of data link interfaces for receiving and outputting data serially, the plurality of data link interfaces synchronized with the clock signal and operable to independently transfer input data or output data between any one of the plurality of data link interfaces and any one of the plurality of memory blocks during non-volatile memory data transfer operations, each of the plurality of data link interfaces having input buffers for receiving the input data and output drivers for driving the output data. - View Dependent Claims (41, 42, 43, 44, 45)
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46. A semiconductor memory device in a chip package comprising:
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a clock input pin in the chip package for receiving a clock signal; a plurality of independently controllable memory blocks; and a plurality of data link interfaces for receiving and outputting in single-bit-wide data streams, the plurality of data link interfaces synchronized with the clock signal and operable to independently transfer input data or output data between any one of the plurality of data link interfaces and any one of the plurality of memory blocks during non-volatile memory data transfer operations, each of the plurality of data link interfaces having input buffers for receiving the input data and output drivers for driving the output data. - View Dependent Claims (47, 48, 49, 50, 51)
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Specification