Method, circuit and system for erasing one or more non-volatile memory cells

• US 7,652,930 B2
• Filed: 04/03/2005
• Issued: 01/26/2010
• Est. Priority Date: 04/01/2004
• Status: Active Grant

• Current Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Original Assignee: Saifun Semiconductors Ltd. (Infineon Technologies AG)
• Inventors: Bloom, Ilan, Eitan, Boaz, Shappir, Assaf
• Primary Examiner(s): Nguyen; Dang T
• Application Number:
  US10/537,857
• Publication Number:
  US 20060056240A1
• Time in Patent Office: 1,759 Days
• Field of Search: 365/185.29, 365/185.22, 365/185.19, 365/185.3, 365/185.33, 365/185.2, 365/185.15, 365/185.18
• US Class Current: 365/185.29
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups

Abstract

The present invention is a method circuit and system for erasing one or more non-volatile memory (“NVM”) cells in an NVM array. One or more NVM cells of a memory array may be erased using an erase pulse produced by a controller and/or erase pulse source adapted to induce and/or invoke a substantially stable channel current in the one or more NVM cells during an erasure procedure. The voltage profile of an erase pulse may be predefined or the voltage profile of the erase pulse may be dynamically adjusted based on feedback from a current sensor during an erase procedure.

Claims

1. A method of erasing one or more non-volatile memory (“

NVM”

) cells comprising;

applying to the one or more NVM cells an erase pulse having a predominantly non-flat and non-linear voltage profile, and wherein said erase pulse has a predefined voltage profile selected from the group consisting of ramp-like, exponential-growth-like, asymptote-like and stepped.

2. The method according to claim 1, wherein the erase pulse is applied to each sub-set of a set of NVM cells in a staggered sequence.

3. The method according to claim 1, wherein the voltage profile of the erase pulse is dynamically adjusted based on feedback.

4. The method according to claim 3, wherein the feedback comes from a sensor selected from the group consisting of a current sensor, a voltage sensor, a current derivative sensor, and a voltage derivative sensor.

5. The method according to claim 4, wherein the voltage of the erase pulse is adjusted in an inverse relation to current measure by the current sensor.

6. The method according to claim 4, wherein the voltage of the erase pulse is adjusted at a rate correlated to a signal produced by the current derivative sensor.

7. A circuit for erasing one or more non-volatile memory (“

NVM”

) cells comprising;

an erase pulse source to produce an erase pulse having a predominantly non-flat and non-linear voltage profile, and wherein said erase pulse source is adapted to produce an erase pulse having a predefined voltage profile selected from the group consisting of ramp-like, exponential-growth-like, asymptote-like and stepped.

8. The circuit according to claim 7, further comprising a cell select circuit adapted to select to which cells of a set of NVM cells the erase pulse is applied.

9. The circuit according to claim 8, wherein said cell select circuit is adapted to apply the erase pulse to each sub-set of the set of NVM cells in a staggered sequence.

10. The circuit according to claim 7, further comprising a sensor to sense a characteristic of the erase pulse as it is being applied to the one or more NVM cells.

11. The circuit according to claim 10, wherein the sensor is selected from the group consisting of a current sensor, a voltage sensor, a current derivative sensor, and a voltage derivative sensor.

12. The circuit according to claim 7, further comprising a controller to cause the erase pulse source to adjust the voltage profile of the erase pulse based on a signal from said sensor.

13. The circuit according to claim 12, wherein said controller causes the voltage of the erase pulse to be adjusted in an inverse relation to current measure by the current sensor.

14. The circuit according to claim 12, wherein said controller causes the voltage of the erase pulse to be adjusted at a rate correlated to a signal produced by the current derivative sensor.

15. A system for erasing one or more non-volatile memory (“

NVM”

) cells comprising;

A NVM array, and an erase pulse source to produce an erase pulse having a predominantly non-flat and non-linear voltage profile, and wherein said erase pulse source is adapted to produce an erase pulse having a predefined voltage profile selected from the group consisting of ramp-like, exponential-growth-like, asymptote-like and stepped.