Method for using a multi-master multi-slave bus for power management

• US 7,653,757 B1
• Filed: 08/05/2005
• Issued: 01/26/2010
• Est. Priority Date: 08/06/2004
• Status: Active Grant

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Zilker Labs LLC (Renesas Electronics Corporation)
• Inventors: Templeton, James W., Wishneusky, John A., Fernald, Kenneth W.
• Primary Examiner(s): Patel; Niketa I
• Assistant Examiner(s): Unelus; Ernest
• Application Number:
  US11/198,698
• Time in Patent Office: 1,635 Days
• Field of Search: 323/282, 323/222, 713/300, 713/340, 710/120, 710/3
• US Class Current: 710/3
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C

Abstract

In one set of embodiments, a power management system comprises two or more devices, such as POL devices, configured to transmit and receive data over a shared bus, such as an I2C bus, according to the bus protocol of the shared bus. Each device may be configured with at least one respective address register, which may be programmed with an address uniquely identifying the device, and a mask register that may be configured to mask select bits of the respective address register, thereby enabling the device to identify device groups. In one embodiment, one of the devices identifying itself as a master device may distribute information to any of the other devices by transmitting the information, which may include commands and/or data, to itself, in effect targeting the address programmed into its own address register. The devices on the shared bus may be configured to monitor the bus for events, and respond to each event according to the requirements inherent within a transmitted command, thereby performing the necessary tasks to enable power management functions without the need for interconnecting analog signal lines.

Claims

1. A system comprising:

a bus configured to operate according to a bus protocol;

a plurality of devices coupled to the bus, wherein the plurality of devices are configured to transmit and receive information over the bus according to the bus protocol, wherein each of the plurality of devices is uniquely identified by corresponding one or more addresses;

wherein a first one of the plurality of devices is configured to initiate a bus operation on the bus, by placing a specified address of the one or more addresses that uniquely identifies the first one of the plurality of devices onto the bus, wherein the specified address is the initial address placed onto the bus;

wherein the bus operation comprises transmitting specified information onto the bus;

wherein at least a second one of the plurality of devices is configured to receive the specified address and the specified information, and utilize the specified information to perform one or more functions in response to receiving the specified address;

wherein at least a subset of the plurality of devices constitutes a group;

wherein for any given device in the group each one of the one or more addresses that uniquely identifies the given device comprises a respective first segment of bits and a respective second segment of bits;

wherein each respective first segment of bits specifies the group;

wherein each respective second segment of bits specifies the given device within the group;

wherein each device of the group comprises;

an address register configured to store at least one of the one or more addresses that uniquely identifies the device; and

a mask register configured to mask out at least a portion of the address register wherein the portion corresponds to the respective second segment of bits of the at least one of the one or more addresses that uniquely identifies the device.

2. The system of claim 1, wherein the plurality of devices comprises point-of-load (POL) converters and the one or more functions comprise power management functions.

3. The system of claim 1, wherein the bus is one of:

an Inter-IC (I2C) bus; and

a System Management Bus (SMBus).

4. The system of claim 1, wherein the bus operation is a bus write operation or a bus read operation.

5. The system of claim 1, further comprising a local controller coupled to the bus and configured to individually access and control each of the plurality of devices through the bus.

6. The system of claim 5, wherein the plurality of devices comprises point-of-load (POL) devices;

the system further comprising non-POL devices coupled to the bus;

wherein the local controller is configured to access and control each of the non-POL devices through the bus.

7. The system of claim 6, wherein the one or more addresses that uniquely identify each of the plurality of devices comprise a respective first address and a respective second address for each of the plurality of devices;

wherein the specified address is the respective first address of the first device; and

wherein in individually accessing and controlling any given one of the plurality of devices through the bus, the local controller is configured to use the respective second address of the given one of the plurality of devices.

8. A method for communicating over a shared bus, the method comprising:

a first device of a plurality of devices initiating a bus operation over the shared bus, wherein said initiating the bus operation comprises;

transmitting over the shared bus a specified address that uniquely identifies the first device;

transmitting data onto the shared bus; and

a second device of the plurality of devices receiving the specified address and the data, and utilizing the data to perform one or more functions in response to at least a first portion of the specified address;

wherein at least the first device and the second device of the plurality of devices constitutes a group;

wherein for any given device in the group, each one of the one or more addresses that uniquely identifies the given device comprises a respective first segment of bits and a respective second segment of bits;

wherein each respective first segment of bits specifies the group;

wherein each respective second segment of bits specifies the given device within the group;

wherein each device of the group comprises;

an address register configured to store at least one of the one or more addresses that uniquely identifies the device; and

a mask register configured to mask out at least a portion of the address register wherein the portion corresponds to the respective second segment of bits of the at least one of the one or more addresses that uniquely identifies the device.

9. The method of claim 8, wherein said transmitting data onto the shared bus is performed during time periods when, according to the bus protocol, data transmitted onto the shared bus is not required to remain stable.

10. The method of claim 8, wherein said transmitting the data is performed in data bursts.

11. The method of claim 8, wherein the first device is a master device and the specified address that uniquely identifies the first device identifies the master device, wherein the second device and remaining ones of the plurality of devices are slave devices;

the method further comprising one or more of;

the master device responding to the first portion of the specified address; and

one or more slave devices responding to the first portion of the specified address.

12. The method of claim 11, wherein the bus operation is a write operation comprising the master device transmitting information onto the shared bus;

the method further comprising one or more of;

the one or more slave devices receiving the information;

the one or more slave devices transmitting data onto the shared bus according to the information;

the one or more slave devices performing one or more functions according to the information;

the master device transmitting data onto the shared bus according to the information; and

the master device performing one or more functions according to the information.

13. The method of claim 11, wherein the bus operation is a write operation comprising the master device transmitting master power status information onto the shared bus;

the method further comprising;

the one or more slave devices receiving the master power status information; and

each respective slave device of the one or more slave devices transmitting respective slave power status information onto the shared bus.

14. The method of claim 11, wherein the bus operation is a write operation comprising the master device transmitting a synchronization command;

the method further comprising;

the one or more slave devices receiving the synchronization command;

the master device successively transmitting a start event, the specified address, synchronization data, and a stop event;

each respective slave device of the one or more slave devices successively receiving the start event, the specified address, the synchronization data, and the stop event;

the master device measuring a transmission time period elapsed between the transmission of the start event and the transmission of the stop event; and

each respective slave device of the one or more slave devices measuring a respective reception time period elapsed between the reception of the start event by the respective slave device and the reception of the stop event by the respective slave device.

15. The method of claim 14, wherein the master device comprises a master oscillator and each respective slave device of the one or more slave devices comprises a respective slave oscillator;

the method further comprising;

the master device successively transmitting a timing result command and data representing the transmission time period;

the one or more slave devices receiving the timing result command and the data representing the transmission time period;

each respective slave device of the one or more slave devices synchronizing its respective slave oscillator to the master oscillator according to its respective reception time period and the transmission time period.

16. The method of claim 11, wherein the bus operation is a write operation comprising the master device transmitting a group exchange command;

the method further comprising;

the one or more slave devices receiving the group exchange command;

the master device successively transmitting a start event and the specified address as part of a read command;

the master device writing respective first data to the shared bus;

the one or more slave devices successively writing respective data to the shared bus in an order determined by respective addresses uniquely identifying each of the one or more slave devices; and

the master device transmitting a stop event.

17. A power management system configured to allow digital information corresponding to power management functions to be passed between point-of-load (POL) converters using a standard multi-master multi-slave interface, the system comprising:

a shared bus;

a plurality of POL converters coupled to the shared bus, wherein each of the plurality of POL converters is configured to transmit and receive information over the shared bus according to a bus protocol corresponding to the shared bus, wherein each of the plurality of POL converters is configured to be uniquely identified by respective one or more addresses;

wherein at least one of the plurality of POL converters is configured to identify itself as a master POL converter, wherein the master POL converter is configured to initiate a bus operation on the shared bus, by placing a specified address of the respective one or more addresses that uniquely identify the master POL converter onto the bus, and wherein the master POL converter is further configured to transmit specified information onto the shared bus as part of the bus operation;

wherein remaining respective ones of the plurality of POL converters are configured to identify themselves as respective slave POL converters, wherein the respective slave POL converters are configured to receive the specified address and the specified information, and utilize the specified information to perform one or more functions in response to receiving the specified address;

wherein the plurality of POL converters are comprised in a group;

wherein a first segment of bits of at least a first respective address of each of the respective one or more addresses identifies the group;

wherein a second segment of bits of at least the first respective address identifies a respective one of the plurality of POL converters within the group;

wherein each respective one of the plurality of POL converters within the group comprises;

a respective address register configured to store the respective first address of the respective one of POL converters; and

a respective mask register configured to mask out at least a portion of the respective address register, wherein the portion corresponds to the second segment of bits, thereby identifying the respective one of the POL converters as being part of the group.

18. The power management system of claim 17, wherein the respective first address of each respective one of the plurality of POL converters is assigned according to one or more operational configurations of the plurality of POL converters.

19. The power management system of claim 18, wherein the one or more operational configurations comprise:

a sequencing order of the plurality of POL converters; and

a phase offset of each respective one of the plurality of POL converters.

20. The power management system of claim 17;

wherein the shared bus is one of;

an Inter-IC (I2C) bus; and

a System Management Bus (SMBus); and

wherein the bus operation is one of;

a bus write operation; and

a bus read operation.

21. The power management system of claim 17;

wherein the specified information comprises a specified power management command;

wherein the slave POL converters are configured to perform a power management function corresponding to the power management command.

22. The power management system of claim 21, wherein the master POL converter is configured to perform a power management function corresponding to the specified power management command.

23. A system comprising:

a shared bus;

a plurality of point-of-load (POL) converters coupled to the shared bus, wherein each respective one of the plurality of POL converters is configured to;

initiate one or more events on the shared bus by transmitting its own address onto the shared bus, thereby also identifying itself to other ones of the plurality of POL converters;

after initiating each respective event, as part of the respective event transmit a respective command corresponding to a respective one of a plurality of power management functions;

monitor the shared bus for the transmitted own address; and

respond to the one or more respective events over the shared bus in response to recognizing the transmitted own address, wherein in responding to each respective event, the respective one of the plurality of POL converters is configured to respond according to the respective command, thereby performing one or more tasks corresponding to the respective one of the plurality of power management functions;

wherein at least a subset of the plurality of POL converters constitutes a group;

wherein for any given POL converter in the group the own address of the given POL converter comprises a respective first segment of bits and a respective second segment of bits;

wherein each respective first segment of bits specifies the group;

wherein each respective second segment of bits specifies the given POL converter within the group;

wherein each POL converter of the group comprises;

an address register configured to store the own address of the POL converter; and

a mask register configured to mask out at least a portion of the address register wherein the portion corresponds to the respective second segment of bits of the own address of the POL converter.

24. A device comprising:

a bus interface configured to interface to a bus;

a first memory element configured to store a first identifier that uniquely identifies the device, wherein a first portion of the first identifier identifies a first group wherein the device and one or more other devices are included in the first group, wherein a remaining portion of the first identifier identifies the device within the first group; and

a second memory element configured to store masking information corresponding to the first identifier, wherein the masking information masks the remaining portion of the first identifier;

wherein the device is configured to communicate with the one or more other devices through the bus interface by initiating a bus operation intended for the bus by transmitting the first identifier through the bus interface, wherein the first identifier uniquely identifies the device as a source of the bus operation, wherein the first portion of the first identifier also specifies the one or more other devices as targets of the bus operation.

25. The device of claim 24, wherein the first group is defined by a plurality of values, wherein the device and the one or more other devices are each uniquely identified by a respective one of the plurality of values.

26. The device of claim 25, wherein the plurality of values form an address range, wherein each one of the plurality of values is an address.

27. The device of claim 24, wherein the device is uniquely identified by a plurality of identifiers that includes the first identifier.

28. The device of claim 27, wherein a respective first portion of each of the plurality of identifiers identifies a respective one of a plurality of groups, wherein the device is included in the identified ones of the plurality of groups.

29. The device of claim 28, wherein each of the one or more of the other devices is included in one or more of the identified ones of the plurality of groups.

30. The device of claim 28, wherein a respective second portion of each one of the plurality of identifiers identifies the device within the respective one of the plurality of groups identified by the respective first portion of the one of the plurality of identifiers.

31. A method for communicating over a bus, the method comprising:

a first device coupled to the bus initiating a bus operation by transmitting, to the bus, a first address that uniquely identifies the first device;

the first device transmitting data onto the bus as part of the bus operation; and

a subset of remaining devices that are coupled to the bus receiving the first address and the data, and utilizing the data to perform one or more functions in response to receiving the first address;

wherein the first device and the subset of the remaining devices constitutes a group;

wherein each given device of the group comprises;

an address register configured to store a respective address that uniquely identifies the given device, wherein the respective address comprises a respective first segment of bits and a respective second segment of bits, wherein the respective first segment of bits specifies the group and wherein the respective second segment of bits specifies the given device within the group; and

a mask register configured to mask out at least a portion of the address register wherein the portion corresponds to the respective second segment of bits of the respective address that uniquely identifies the given device.

32. The method of claim 31, wherein the bus operation includes the first device transmitting a value onto the bus, wherein the subset of the remaining devices responding to the bus operation comprises one or more of the subset of the remaining devices storing the value transmitted by the first device.

33. The method of claim 31, wherein the subset of the remaining devices utilizing the data to perform one or more functions comprises one or more of the subset of the remaining devices initiating a second bus operation over the bus.

34. The method of claim 31, wherein said transmitting data onto the bus is performed during time periods when, according to the bus protocol, data transmitted onto the bus is not required to remain stable.

35. The method of claim 34, wherein said transmitting the data is performed in data bursts.

36. The method of claim 31, wherein the first device is a master device, wherein the subset of the remaining devices is a group of slave devices, wherein the method further comprises at least one of the group of slave devices responding to the bus operation according to the first segment of bits of the first address.

37. The method of claim 36, further comprising the master device responding to the bus operation according to the first segment of bits of the first address.

38. A device comprising:

a bus interface configured to interface to a bus; and

a first memory element configured to store a first address that uniquely identifies the device, wherein the first address comprises;

a first segment of bits that specifies a group; and

a second segment of bits that specifies the device within the group; and

a second memory element configured to mask out at least a portion of the address register, wherein the portion corresponds to the second segment of bits;

wherein the device is configured to initiate bus transactions intended for the bus, and communicate with other devices via the bus interface by transmitting information packets and receiving information packets from the other devices through the bus interface;

wherein in initiating the bus transactions the device is configured to transmit the first address through the bus interface as a target address for the bus transactions; and

wherein at least one of the other devices is configured to receive the first address and the information packets, and utilize information from the information packets to perform one or more functions in response to receiving the first address.

39. A device comprising:

a bus interface configured to interface to a bus, wherein the device is operable to communicate with other devices via the bus interface;

a first register configured to store a first address that uniquely identifies the device; and

a second register configured as a mask register for the first register wherein an unmasked segment of bits of the first address defines an address group, wherein a masked segment of bits of the first address identifies the device within the address group;

wherein the device and at least one of the other devices are comprised in the address group;

wherein the device configured to initiate a bus operation intended for the bus by transmitting the first address and data through the bus interface, wherein the first address is transmitted as a target address for the bus operation; and

wherein at least one of the other devices is configured to receive the first address and the data, and utilize at least a portion of the data to perform one or more functions in response to receiving the first address.

40. The device of claim 39, further comprising a first plurality of additional registers, each of the first plurality of registers configured to store a respective address that uniquely identifies the device.

41. The device of claim 40, further comprising a second plurality of registers, each of the second plurality of registers configured as a mask register for a respective one of the first plurality of registers, wherein a respective unmasked segment of bits of each respective address defines an additional respective address group, wherein the device and at least a subset of the other devices are comprised in the additional respective address group.

42. The device of claim 41, wherein a masked respective segment of bits of each respective address identifies the device within the additional respective address group.