Resource sharing in multiple parallel pipelines

• US 7,653,804 B2
• Filed: 01/26/2006
• Issued: 01/26/2010
• Est. Priority Date: 01/26/2006
• Status: Expired due to Fees

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Lenart, Thomas A., Janneck, Jorn W.
• Primary Examiner(s): Chan; Eddie P
• Assistant Examiner(s): Vicary; Keith
• Application Number:
  US11/340,279
• Publication Number:
  US 20070174593A1
• Time in Patent Office: 1,461 Days
• Field of Search: 712/25, 712/201, 712/23, 712/18, 712/26
• US Class Current: 712/18
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding

Abstract

A signal processing network and method for generating code for such a signal processing network are described. Pipeline blocks are each coupled to receive control signaling and associated information signaling from a scheduler. Each of the pipeline blocks respectively includes an allocation unit, a pipeline, and section controllers. The allocation unit is configured to provide a lock signal and sequence information to the section controllers in each of the pipeline blocks. The section controllers are configured to maintain in order inter-pipeline execution of the sequence responsive to the sequence information and the lock signal.

Claims

1. A signal processing network, comprising:

pipeline blocks implemented in hardware and in parallel;

each of the pipeline blocks coupled to receive control signaling and information signaling from a scheduler;

the scheduler being a dataflow device coupled to receive data for providing the control signaling and the information signaling;

the scheduler configured to receive tokens from respective first-in, first-out buffers, the tokens being amounts of data;

the control signaling indicating validity of the data of the information signaling;

each pipeline block of the pipeline blocks including an allocation unit, a pipeline, and section controllers;

the pipeline sectioned into one or more stages, the section controllers being serially coupled to one another with each stage of the one or more stages being between two consecutive ones of the section controllers such that each entry boundary and exit boundary of each said stage of the one or more stages is controlled by the section controllers;

the pipeline coupled to receive an information signal of the information signaling from the scheduler;

the allocation unit coupled to receive a control signal of the control signaling from the scheduler;

the control signal being one of a sequence of control signals of the control signaling;

the control signal being for loading of data of an information signal of the information signaling into the pipeline in the pipeline block having the allocation unit which receives the control signal;

the allocation unit configured to provide a lock signal to the section controllers in each of the pipeline blocks, the lock signal indicating that resources targeted for use by the pipeline associated with the allocation unit are being locked;

the allocation unit configured to provide sequence information indicating a position in the sequence to the section controllers of the pipeline block associated with the allocation unit;

the sequence information including a wave number and a sequence number;

the wave number being associated with a data wave currently in the pipeline block associated with the allocation unit issuing the wave number;

the sequence number being incremented above the wave number to indicate a next wave number for scheduling a next data wave for the pipeline block associated with the allocation unit issuing the sequence number;

the section controllers configured to maintain in order inter-pipeline block execution among the pipeline blocks responsive to the sequence information and the lock signal and configured to provide unlock signaling;

each of the section controllers configured to compare the wave number to the sequence number;

wherein a section controller of the section controllers is configured to determine from such comparison whether to allow the data wave to pass into a stage of the one or more stages associated with the pipeline block having the section controller for in-sequence processing of multiple data waves among the pipeline blocks;

the resources being shared resources among two or more of the pipeline blocks; and

the section controllers of the pipeline block configured to provide locking and unlocking signaling for inter-pipeline control for access to the shared resources without locking or unlocking the shared resources themselves.

2. The signal processing network according to claim 1, wherein a lock state of a shared resource of the shared resources is stored in a section controller of the section controllers asserting a lock thereof.

3. The signal processing network according to claim 1, wherein the section controllers are configured to unlock the shared resources when the shared resources become available.

4. The signal processing network according to claim 3, wherein a section controller of the section controllers of the pipeline block provides the unlock signaling to the section controllers remaining in each of the pipeline blocks for inter-pipeline control.

5. The signal processing network according to claim 4, wherein the control signal is provided from the allocation unit to each of the section controllers within the pipeline block in which the allocation unit is located.

6. The signal processing network according to claim 5, wherein the sequence information is provided to each of the section controllers within the pipeline block in which the allocation unit that receives the control signal is associated.

7. The signal processing network according to claim 6, wherein the signal processing network is disposed in an integrated circuit.

8. The signal processing network according to claim 7, wherein the integrated circuit is a programmable logic device, wherein each of the pipeline blocks is instantiated in programmable logic of the programmable logic device.