Method and apparatus for adaptive power consumption

• US 7,653,825 B1
• Filed: 06/13/2006
• Issued: 01/26/2010
• Est. Priority Date: 08/22/2002
• Status: Active Grant

• Current Assignee: Nokia Solutions and Networks US LLC (Nokia Corporation)
• Original Assignee: NVIDIA Corporation
• Inventors: White, Jonathan B., van Welzen, James L.
• Primary Examiner(s): CHEN, TSE W
• Application Number:
  US11/452,462
• Time in Patent Office: 1,323 Days
• Field of Search: 713/322, 713/323, 713/324
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method for adapting power consumption of a processor based upon an application demand is provided. The method initiates with determining an application demand based upon a current processing operation. Then, a time interval associated with the application demand is determined. Next, unnecessary power consuming functions for the application demand are determined. Then, a clock frequency for the unnecessary power consuming functions is reduced for the time interval. In one embodiment, the power is terminated to the unnecessary power consuming functions. In another embodiment, the clock frequency of the processor is adjusted for at least a portion of the time interval. A program interface for adapting power consumption of a computer system, processor instructions for adapting power consumption of a computer system and a processor are included.

Claims

1. A system comprising:

a processor including a control register for controlling power consumption of the processor;

one or more computer readable medium for storing an application;

a power adjusting interface including a hook to the application being executed by the processor, wherein the application communicates a future demand of the application to the power adjusting interface, and wherein the power adjusting interface determines a time interval associated with the future demand from a table that associates the future demand of the application to a corresponding time interval, determines unnecessary power consuming functions within the processor based on the future demand and writes data to the control register based on the future demand, time interval and unnecessary power consuming functions to control power consumption of the processor.

2. The system of claim 1, wherein the processor is selected from the group consisting of a central processing unit (CPU), a graphics processing unit (GPU), network processing unit (NPU) and a storage processing unit (SPU).

3. The system of claim 1 wherein the processor is a component of a portable computing device.

4. The system of claim 1, wherein the power adjusting interface including the hook to the application comprises an application program interface (API).

5. The system of claim 1, wherein the power adjusting interface including the hook to the application comprises an operating system (OS) interface.

6. A system comprising:

a processor including a control register for controlling power consumption of the processor;

one or more computer readable medium for storing an application including one or more frames of one or more types;

a power adjusting interface including a hook to the application being executed on the processor, wherein the application communicates a future per-frame demand of the application to the power adjusting interface, and wherein the power adjusting interface determines a time interval associated with the future per-frame demand from a table that associates the future per-frame demand of the application to a corresponding time interval, determines unnecessary power consuming functions within the processor for the time interval and the future per-frame demand and writes data to the control register based on the future per frame demand, the time interval and the unnecessary power consuming function to control a clock speed of the processor and a plurality of power consuming functions of the processor.

7. The system of claim 6, wherein the processor is selected from the group consisting of a central processing unit (CPU), a graphics processing unit (GPU), network processing unit (NPU) and a storage processing unit (SPU).

8. The system of claim 6 wherein the processor is a component of a portable computing device.

9. The system of claim 6, wherein the power adjusting interface including the hook to the application comprises an application program interface (API).

10. The processor of claim 6, wherein the power adjusting interface including the hook to the application comprises an operating system (OS) interface.