Phase shifter with reduced linear dependency

• US 7,653,851 B2
• Filed: 03/26/2009
• Issued: 01/26/2010
• Est. Priority Date: 11/23/1999
• Status: Expired due to Fees

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Tyszer, Jerzy, Rajski, Janusz, Tamarapalli, Nagesh
• Primary Examiner(s): Ton; David
• Application Number:
  US12/412,267
• Publication Number:
  US 20090187800A1
• Time in Patent Office: 306 Days
• Field of Search: 365/244, 380/28, 711/100, 382/276, 326/46, 714/726, 714/739, 714/729, 714/727
• US Class Current: 714/729
• CPC Class Codes: G01R 31/31813 Test pattern generators
• CPC Class Codes: G01R 31/318385 Random or pseudo-random test pattern
• CPC Class Codes: G01R 31/318541 Scan latches or cell details
• CPC Class Codes: G01R 31/318547 Data generators or compressors
• CPC Class Codes: G01R 31/318594 Timing aspects clock circuits G01R31/318552

Abstract

A method is disclosed for the automated synthesis of phase shifters—circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.

Claims

1. A method of creating a pseudo-random pattern generator used to generate test patterns in a built-in self-test framework, comprising:

generating a linear feedback shift register including multiple flip-flops coupled in a ring structure with feedback connections between the flip-flops and with output taps that provide a pseudo-random pattern; and

generating a phase shifter coupled to the linear feedback shift register, the phase shifter including multiple XOR or XNOR gates, wherein generating the phase shifter includes storing loading information on each output tap of the linear feedback shift register and coupling the output taps to the XOR or XNOR gates of the phase shifter by ensuring that the output taps are not used if their respective loading exceeds a predetermined limit.

2. The method of claim 1, wherein generating the linear feedback shift register includes generating successive output tap combinations randomly and then determining whether the generated output tap combinations can be accepted based on a predetermined interchannel separation criterion that is not smaller than a predetermined value.

3. The method of claim 2, wherein determining whether the generated output tap combinations can be accepted includes simulating to ensure that each sequence of patterns generated by the linear feedback shift register are shifted with respect to every other sequence by at least a pre-specified number of bits.

4. The method of claim 1, wherein ensuring that output taps are not used if their respective loading exceeds a predetermined limit includes using a histogram to track loading of the flip-flops.

5. The method of claim 1, wherein generating the phase shifter includes selecting flip-flops of the linear feedback shift register by using a pseudo-random number generator yielding uniformly distributed integers between 0 and n-1, wherein n represents the size of the linear feedback shift register.

6. The method of claim 1, wherein generating the phase shifter comprises ensuring that there is a substantially balanced load across the output taps.

7. The method of claim 1, further including generating test patterns to be loaded in scan chains coupled to the phase shifter.

8. The method of claim 7, further including ensuring a phase shift of the test patterns from the linear phase shifter outputs is greater than a length of the longest scan chain.

12. The method of claim 1, wherein generating the linear feedback shift register includes generating successive output tap combinations randomly and then determining whether the generated output tap combinations can be accepted based on a predetermined interchannel separation criterion that is not smaller than a predetermined value.

13. The method of claim 12, wherein determining whether the generated output tap combinations can be accepted includes simulating to ensure that each sequence of patterns generated by the linear feedback shift register are shifted with respect to every other sequence by at least a pre-specified number of bits.

9. An apparatus to generate test patterns in a built-in self-test framework, comprising:

a linear feedback shift register including multiple flip-flops coupled in a ring structure with feedback connections between the flip-flops and with output taps that provide a pseudo-random pattern; and

a phase shifter coupled to the linear feedback shift register, the phase shifter including multiple XOR or XNOR gates coupled to the output taps of the linear feedback shift register, wherein the number of XOR or XNOR gates coupled to the output taps is substantially equal in number.

10. The apparatus of claim 9 further including a plurality of scan chains coupled to the phase shifter, the scan chains including a series combination of flip-flops.

11. A method of creating a pseudo-random pattern generator used to generate test patterns in a built-in self-test framework, comprising:

generating a linear feedback shift register including multiple flip-flops coupled in a ring structure with feedback connections between the flip-flops and with output taps that provide a pseudo-random pattern; and

generating a phase shifter including multiple XOR or XNOR gates, wherein generating the phase shifter includes distributing the connections between the XOR and XNOR gates and the output taps so as to achieve balanced loading on the output taps.

14. The method of claim 11, further including using a histogram to track loading of the flip-flops.

15. The method of claim 11, wherein generating the phase shifter includes selecting flip flops of the linear feedback shift register by using a pseudo-random number generator yielding uniformly distributed integers between 0 and n-1, wherein n represents the size of the linear feedback shift register.

16. The method of claim 11, wherein balanced loading includes having substantially a same number of XOR or XNOR gates coupled to the output taps.

17. The method of claim 11, further including generating test patterns to be loaded in scan chains coupled to the phase shifter.

18. The method of claim 17, further including ensuring a phase shift of the test patterns from the linear phase shifter outputs is greater than a length of the longest scan chain.