Access control apparatus, access control system, processor, access control method, memory access control apparatus, memory access control system, and memory access control method
First Claim
1. An access control apparatus to control an access among a writer, a reader, and a memory, comprising:
- a parity generator that generates a parity of write data to be written in the memory;
a parity adder that adds the parity to the write data to generate parity-added data;
a writer syndrome generator that generates a writer syndrome of writer mask data to mask the parity-added data, the writer syndrome being associated with a writer access ID used when the writer accesses the memory, the writer requesting writing of the write data into the memory;
a write mask generator that generates the writer mask data based on the writer syndrome, the writer access ID, and a write address in the memory at which the writer writes the write data;
a first XOR calculator that obtains first post-operation data by calculating an XOR between the parity-added data and the writer mask data;
a write address converter that converts the write address into another address determined by the writer access ID;
a write unit that writes the first post-operation data to the address converted by the write address converter;
a reader syndrome generator that generates a reader syndrome of reader mask data to mask the first post-operation data, the reader syndrome being associated with a reader access ID used when the reader accesses the memory, the reader requesting reading of data from the memory;
a reader mask generator that generates the reader mask data based on the reader syndrome, the reader access ID, and a read address in the memory at which the reader reads the read data from;
a read address converter that converts the read address into another address determined based on the reader access ID;
a read unit that reads the first post-operation data from the address converted by the read address converter;
a second XOR calculator that obtains second post-operation data by calculating an XOR between the reader mask data and the first post-operation data;
a data syndrome calculator that calculates an actual data syndrome from the second post-operation data; and
an output determining unit that determines whether the second post-operation data is to be output as the read data which is requested by the reader to read, based on the actual data syndrome.
1 Assignment
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Accused Products
Abstract
An access control apparatus includes a writer syndrome generator that generates a writer syndrome of writer mask data to mask the parity-added data, the writer syndrome being associated with a writer access ID used when a writer that requests writing of the write data in the memory accesses the memory; a write mask generator that generates the writer mask data based on the writer syndrome, the writer access ID, and a write address in the memory at which the writer writes the write data; a first XOR calculator that obtains first post-operation data by calculating an XOR between the parity-added data and the writer mask data; and a write address converter that converts the write address into another address determined by the writer access ID.
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Citations
16 Claims
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1. An access control apparatus to control an access among a writer, a reader, and a memory, comprising:
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a parity generator that generates a parity of write data to be written in the memory; a parity adder that adds the parity to the write data to generate parity-added data; a writer syndrome generator that generates a writer syndrome of writer mask data to mask the parity-added data, the writer syndrome being associated with a writer access ID used when the writer accesses the memory, the writer requesting writing of the write data into the memory; a write mask generator that generates the writer mask data based on the writer syndrome, the writer access ID, and a write address in the memory at which the writer writes the write data; a first XOR calculator that obtains first post-operation data by calculating an XOR between the parity-added data and the writer mask data; a write address converter that converts the write address into another address determined by the writer access ID; a write unit that writes the first post-operation data to the address converted by the write address converter; a reader syndrome generator that generates a reader syndrome of reader mask data to mask the first post-operation data, the reader syndrome being associated with a reader access ID used when the reader accesses the memory, the reader requesting reading of data from the memory; a reader mask generator that generates the reader mask data based on the reader syndrome, the reader access ID, and a read address in the memory at which the reader reads the read data from; a read address converter that converts the read address into another address determined based on the reader access ID; a read unit that reads the first post-operation data from the address converted by the read address converter; a second XOR calculator that obtains second post-operation data by calculating an XOR between the reader mask data and the first post-operation data; a data syndrome calculator that calculates an actual data syndrome from the second post-operation data; and an output determining unit that determines whether the second post-operation data is to be output as the read data which is requested by the reader to read, based on the actual data syndrome. - View Dependent Claims (2, 3, 4)
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5. An access control apparatus to control an access among a writer, a reader, a cache memory, and a memory, comprising:
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a read request receiver that acquires a read address from a reader; a cache monitor that determines whether the read address acquired by the read request receiver is stored in the cache memory, where the cache memory stores data requested by the writer or the reader, an address of the data, and a requester access ID used when the writer or the reader capable of accessing the data accesses the memory, the data, the address, and the requester access ID being associated with each other; a reader syndrome generator that generates a reader syndrome of the reader mask data to mask the data stored in the memory, the reader syndrome being associated with the reader access ID used when the reader accesses the memory, when the cache monitor determines that the read address acquired by the read request receiver is not stored in the cache memory; a reader mask generator that generates the reader mask data based on the reader syndrome, the reader access ID, and the read address; a read address converter that converts the address acquired by the read request receiver to another address determined by the reader access ID; a read unit that reads first post-operation data subjected to a predetermined calculation to the data from the address converted by the read address converter; a first XOR calculator that obtains second post-operation data by calculating an XOR between the reader mask data and the first post-operation data read by the read unit; a data syndrome calculator that calculates an actual data syndrome from the second post-operation data; and an output determining unit that determines whether the second post-operation data is output as the data which is requested by the reader to be read, based on the actual data syndrome. - View Dependent Claims (6, 7, 8, 9)
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10. An access control system comprising:
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a processor; a memory controller; and a memory access control apparatus that controls access to a memory, wherein the memory access control apparatus includes; a parity generator that generates a parity of write data to be written in the memory; a parity adder that adds the parity to the write data to generate parity-added data; a writer syndrome generator that generates a writer syndrome of writer mask data to mask the parity-added data, the writer syndrome being associated with a writer access ID used when a writer accesses the memory, the writer requesting writing of the write data into the memory; a write mask generator that generates the writer mask data based on the writer syndrome, the writer access ID, and a write address in the memory at which the writer writes the write data; a first XOR calculator that obtains first post-operation data by calculating an XOR between the parity-added data and the writer mask data; a write address converter that converts the write address into another address determined by the writer access ID; a write unit that writes the first post-operation data to the address converted by the write address converter; a reader syndrome generator that generates a reader syndrome of reader mask data to mask the first post-operation data, the reader syndrome being associated with a reader access ID used when a reader accesses the memory, the reader requesting reading of data from the memory; a reader mask generator that generates the reader mask data based on the reader syndrome, the reader access ID, and a read address at which the reader data is to be read; a read address converter that converts the read address into another address determined based on the reader access ID; a read unit that reads the first post-operation data from the address converted by the read address converter; a second XOR calculator that obtains second post-operation data by calculating an XOR between the reader mask data and the first post-operation data; a data syndrome calculator that calculates an actual data syndrome from the second post-operation data; and an output determining unit that determines whether the second post-operation data is to be output as the read data which is requested by the reader to read, based on the actual data syndrome.
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11. An access control system comprising:
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a processor; and a memory access control apparatus that controls access to a memory, wherein the memory access control apparatus includes; a parity generator that generates a parity of write data to be written in the memory; a parity adder that adds the parity generated by the parity generator to the write data to generate parity-added data; a writer syndrome generator that generates a writer syndrome of writer mask data to mask the parity-added data, the writer syndrome being associated with a writer access ID used when a writer accesses the memory, the writer requesting writing of the write data into the memory; a write mask generator that generates the writer mask data based on the writer syndrome, the writer access ID, and a write address in the memory at which the writer writes the write data; a first XOR calculator that obtains first post-operation data by calculating an XOR between the parity-added data and the writer mask data; a write address converter that converts the write address into another address determined by the writer access ID; a write unit that writes the first post-operation data to the address converted by the write address converter; a reader syndrome generator that generates a reader syndrome of reader mask data to mask the first post-operation data, the reader syndrome being associated with a reader access ID used when a reader accesses the memory, the reader requesting reading of data from the memory; a reader mask generator that generates the reader mask data based on the reader syndrome, the reader access ID, and a read address at which the reader data is to be read; a read address converter that converts the read address into another address determined based on the reader access ID; a read unit that reads the first post-operation data from the address converted by the read address converter; a second XOR calculator that obtains second post-operation data by calculating an XOR between the reader mask data and the first post-operation data; a data syndrome calculator that calculates an actual data syndrome from the second post-operation data; and an output determining unit that determines whether the second post-operation data is to be output as the read data which is requested by the reader to read, based on the actual data syndrome.
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12. An access control system comprising:
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a processor; a memory controller; and a memory access control apparatus that controls access to a memory, wherein the memory access control apparatus includes; a read request receiver that acquires data to be read from the memory, and a read address of the data from a reader which requests read out of data from the memory; a cache monitor that determines whether the read address acquired by the read request receiver is stored in a cache memory, where the cache memory stores data requested by a writer which requests data to be written in the memory or the reader, an address of the data, and a requester access ID used when the writer or the reader capable of accessing the data accesses the memory, the data, the address, and the requester access ID being associated with each other; a reader syndrome generator that generates a reader syndrome of the reader mask data to mask the data stored in the memory, the reader syndrome being associated with the reader access ID used when the reader accesses the memory, when the cache monitoring unit determines that the read address acquired by the read request receiver is not stored in the cache memory; a reader mask generator that generates the reader mask data based on the reader syndrome, the reader access ID, and the read address; a read address converter that converts the address acquired by the read request receiver to another address determined by the reader access ID; a read unit that reads first post-operation data subjected to a predetermined calculation to the data from the address converted by the read address converter; a first XOR calculator that obtains second post-operation data by calculating an XOR between the reader mask data and the first post-operation data read by the read unit; a data syndrome calculator that calculates an actual data syndrome from the second post-operation data; and an output determining unit that determines whether the second post-operation data is output as the data which is requested by the reader to be read, based on the actual data syndrome.
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13. An access control system comprising:
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a processor; and a memory access control apparatus that controls access to a memory, wherein the memory access control apparatus includes; a read request receiver that acquires data to be read from the memory, and a read address of the data from a reader which requests read out of data from the memory; a cache monitor that determines whether the read address acquired by the read request receiver is stored in a cache memory, where the cache memory stores data requested by a writer which requests data to be written in the memory or the reader, a address of the data, and a requester access ID used when the writer or the reader capable of accessing the data accesses the memory, the data, the address, and the requester access ID being associated with each other; a reader syndrome generator that generates a reader syndrome of the reader mask data to mask the data stored in the memory, the reader syndrome being associated with the reader access ID used when the reader accesses the memory, when the cache monitoring unit determines that the read address acquired by the read request receiver is not stored in the cache memory; a reader mask generator that generates the reader mask data based on the reader syndrome, the reader access ID, and the read address; a read address converter that converts the address acquired by the read request receiver to another address determined by the reader access ID; a read unit that reads first post-operation data subjected to a predetermined calculation to the data from the address converted by the read address converter; a first XOR calculator that obtains second post-operation data by calculating an XOR between the reader-mask data and the first post-operation data read by the read unit; a data syndrome calculator that calculates an actual data syndrome from the second post-operation data; and an output determining unit that determines whether the second post-operation data is output as the data which is requested by the reader to be read, based on the actual data syndrome.
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14. A processor comprising:
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a memory controller; and a memory access control apparatus that controls access to a memory, wherein the memory access control apparatus includes; a parity generator that generates a parity of write data to be written in the memory; a parity adder that adds the parity generated by the parity generator to the write data to generate parity-added data; a writer syndrome generator that generates-a writer syndrome of writer mask data to mask the parity-added data, the writer syndrome being associated with a writer access ID used when a writer accesses the memory, the writer requesting writing of the write data into the memory; a write mask generator that generates the writer mask data based on the writer syndrome, the writer access ID, and a write address in the memory at which the writer writes the write data; a first XOR calculator that obtains first post-operation data by calculating an XOR between the parity-added data and the writer mask data; a write address converter that converts the write address into another address determined by the writer access ID; a write unit that writes the first post-operation data to the address converted by the write address converter; a reader syndrome generator that generates a reader syndrome of reader mask data to mask the first post-operation data, the reader syndrome being associated with a reader access ID used when a reader accesses the memory, the reader requesting reading of data from the memory; a reader mask generator that generates the reader mask data based on the reader syndrome, the reader access ID, and a read address at which the reader data is to be read; a read address converter that converts the read address into another address determined based on the reader access ID; a read unit that reads the first post-operation data from the address converted by the read address converter; a second XOR calculator that obtains second post-operation data by calculating an XOR between the reader mask data and the first post-operation data; a data syndrome calculator that calculates an actual data syndrome from the second post-operation data; and an output determining unit that determines whether the second post-operation data is to be output as the read data which is requested by the reader to read, based on the actual data syndrome.
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15. An access control method to control an access among a writer, a reader, and a memory, comprising:
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generating a parity of write data to be written in the memory; adding the parity generated to the write data to generate parity-added data; generating a writer syndrome of writer mask data to mask the parity-added data, the writer syndrome being associated with a writer access ID used when the writer accesses the memory, the writer requesting writing of the write data into the memory; generating the writer mask data based on the writer syndrome, the writer access ID, and a write address in the memory at which the writer writes the write data; obtaining first post-operation data by calculating an XOR between the parity-added data and the writer mask data; converting the write address into another address determined by the writer access ID; writing the first post-operation data to the address converted; generating a reader syndrome of reader mask data to mask the first post-operation data, the reader syndrome being associated with a reader access ID used when the reader accesses the memory, the reader requesting reading of data from the memory; generating the reader mask data based on the reader syndrome, the reader access ID, and a read address at which the reader data is to be read; converting the read address into another address determined based on the reader access ID; reading the first post-operation data from the address converted; obtaining second post-operation data by calculating an XOR between the reader mask data and the first post-operation data; calculating an actual data syndrome from the second post-operation data; and determining whether the second post-operation data is to be output as the read data which is requested by the reader to read, based on the actual data syndrome.
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16. A memory access control method to control an access among a writer, a reader, and a memory, comprising:
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acquiring data to be read from the memory, and a read address of the data from the reader which requests read out of data from the memory; determining whether the read address is stored in a cache memory, where the cache memory stores data requested by the writer which requests data to be written in the memory or the reader, a address of the data, and a requester access ID used when the writer or the reader capable of accessing the data accesses the memory, the data, the address, and the requester access ID being associated with each other; generating a reader syndrome of the reader mask data to mask the data stored in the memory, the reader syndrome being associated with the reader access ID used when the reader accesses the memory, when the read address is determined not to be stored in the cache memory; generating the reader mask data based on the reader syndrome, the reader access ID, and the read address; converting the address to another address determined by the reader access ID; reading first post-operation data subjected to a predetermined calculation to the data from the address converted; obtaining second post-operation data by calculating an XOR between the reader mask data and the first post-operation data; calculating an actual data syndrome from the second post-operation data; and determining whether the second post-operation data is output as the data which is requested by the reader to be read, based on the actual data syndrome.
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Specification