Semiconductor device having variable parameter selection based on temperature and test method

• US 7,654,736 B1
• Filed: 12/04/2008
• Issued: 02/02/2010
• Est. Priority Date: 04/19/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Agersonn RALL Group LLC (Intellectual Ventures LLC)
• Inventors: Walker, Darryl
• Primary Examiner(s): Verbitsky, Gail
• Assistant Examiner(s): Jagan, Mirellys
• Application Number:
  US12/315,521
• Time in Patent Office: 425 Days
• Field of Search: 374/176, 374/169
• US Class Current: 374/176
• CPC Class Codes: G01K 7/425 Thermal management of integrated systems

Abstract

A semiconductor device that may include temperature sensing circuits is disclosed. The temperature sensing circuits may be used to control various parameters, such as internal regulated supply voltages, internal refresh frequency, a word line low voltage, or the like. In this way, operating specifications of a semiconductor device at worst case temperatures may be met without compromising performance at normal operating temperatures. Each temperature sensing circuit may include a selectable temperature threshold value as well as a selectable temperature hysteresis value. In this way, temperature performance characteristics may be finely tuned. Furthermore, a method of testing the temperature sensing circuits is disclosed in which a current value may be monitored and temperature threshold values and temperature hysteresis values may be thereby determined.

Claims

1. A device, comprising:

a first temperature sensing circuit having a first temperature threshold value and a first temperature hysteresis value, the first temperature sensing circuit including a first variable resistor for providing the first temperature hysteresis value, the first temperature sensing circuit providing a first temperature indication signal; and

a transistor coupled in parallel with the first variable resistor to provide a shunt in response to the first temperature indication signal.

2. The device of claim 1, wherein:

the first variable resistor is coupled to receive a first hysteresis select value.

3. The device of claim 1, further including:

a latch circuit coupled to provide the first temperature indication signal.

4. The device of claim 1, further including:

an enable transistor having a controllable impedance path coupled in series with the first variable resistor between a power supply potential and a reference potential, the enable transistor having a gate terminal coupled to receive a temperature detect enable signal, the temperature detect enable signal having a first logic level and a second logic level and the enable transistor has a high impedance when the temperature detect enable signal has the first logic level and a low impedance with the temperature detect enable signal has the second logic level.

5. The device of claim 1, wherein:

the device is a semiconductor memory device.

6. The device of claim 5, wherein:

the semiconductor device is a dynamic random access memory.

7. The device of claim 1, wherein:

the first variable resistor coupled to receive a first hysteresis select value that sets the first temperature hysteresis value; and

the first hysteresis select value is provided by at least one first hysteresis select register.

8. The device of claim 7, wherein:

the at least one first hysteresis select register is a plurality of first hysteresis select registers.

9. The device of claim 7, wherein:

the at least one hysteresis select register includes a first hysteresis latch circuit.

10. The device of claim 7, wherein:

the at least one first hysteresis select register is coupled to receive a power up detect signal that sets the first hysteresis select value to a predetermined state.

11. The semiconductor device of claim 7, wherein:

the at least one first hysteresis select register is coupled to receive a hysteresis select load signal and the first hysteresis select value is loaded into the at least one hysteresis select register in response to the hysteresis select load signal.

12. The device of claim 7, wherein:

the first hysteresis select value is loaded into the at least one first hysteresis select register from external to the device by a hysteresis select register load operation.

13. The device of claim 12, wherein:

the hysteresis select register load operation includes a register write command.

14. The device of claim 1, wherein:

the first variable resistor is programmable.

15. The device of claim 14, wherein:

the first variable resistor includes a plurality of resistors connected in series, each one of the plurality of resistors including a corresponding transistor having a drain terminal coupled to a first terminal of the one of the plurality of resistors and a source terminal coupled to a second terminal of the one of the plurality of resistors.

16. The device of claim 15, wherein:

the first hysteresis select value includes a plurality of hysteresis setting signals; and

each one of the plurality of transistors coupled to receive one of the plurality of hysteresis setting signals.

17. The device of claim 14, wherein:

the first variable resistor is programmable with programmable links.

18. The device of claim 17, wherein:

the programmable links include fuses.

19. The device of claim 18, wherein:

the programmable links include polysilicon fuses.