Packaged microelectronic devices and methods for packaging microelectronic devices

• US 7,655,500 B2
• Filed: 02/08/2008
• Issued: 02/02/2010
• Est. Priority Date: 04/22/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jiang, Tongbi, Brooks, J. Michael
• Primary Examiner(s): Luu; Chuong A.
• Application Number:
  US12/028,211
• Publication Number:
  US 20080132006A1
• Time in Patent Office: 725 Days
• Field of Search: 438/106, 438/673, 438/110, 438/125, 438/118, 438/114, 438/107, 438/613, 257/720, 257/723, 257/712, 257/719, 257/738, 257/796
• US Class Current: 438/106
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/82031 by chemical means, e.g. etching, anodisation
• CPC Class Codes: H01L 2224/82039 using a laser
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/83192 wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/83 using a layer connector
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

Packaged microelectronic devices and methods for packaging microelectronic devices are disclosed herein. In one embodiment, a method of packaging a microelectronic device including a microelectronic die having a first side with a plurality of bond-pads and a second side opposite the first side includes forming a recess in a substrate, placing the microelectronic die in the recess formed in the substrate with the second side facing toward the substrate, and covering the first side of the microelectronic die with a dielectric layer after placing the microelectronic die in the recess. The substrate can include a thermal conductive substrate, such as a substrate comprised of copper and/or aluminum. The substrate can have a coefficient of thermal expansion at least approximately equal to the coefficient of thermal expansion of the microelectronic die or a printed circuit board.

Claims

1. A method of packaging a microelectronic device including a microelectronic die having an integrated circuit, a first side with a plurality of bond-pads electrically coupled to the integrated circuit, and a second side opposite the first side, the method comprising:

forming a recess in a substrate, the recess extending into the substrate from a substrate surface;

placing the microelectronic die in the recess formed in the substrate with the second side facing toward the substrate;

placing electric couplers on the individual bond-pads of the microelectronic die, the individual electric couplers having a first end on the bond-pads of the microelectronic die and a second end opposite the first end; and

covering the electric couplers, the first side of the microelectronic die, and the substrate with a dielectric layer after placing the microelectronic die in the recess, the dielectric layer having a first portion over the microelectronic die and the electric couplers and a second portion in the recess, the first portion of the dielectric layer having a first surface proximate to the substrate surface and a second surface opposite the first surface, the first portion of the dielectric layer having a thickness between the first and second surfaces, the thickness being approximately equal to a height of the electric couplers between the first and second ends.

2. The method of claim 1, further comprising forming a conductive link on the dielectric layer, the conductive link being in direct contact with the electric couplers.

3. The method of claim 1, further comprising disposing a conductive link in the dielectric layer that is electrically coupled to at least one of the plurality of bond-pads.

4. The method of claim 1 wherein forming the recess in the substrate comprises removing material from the substrate.

5. The method of claim 1 wherein the substrate comprises a thermally conductive substrate, and wherein forming the recess in the substrate comprises forming a depression in the thermally conductive substrate.

6. The method of claim 1 wherein the substrate comprises a thermally conductive substrate comprised of copper, and wherein forming the recess in the substrate comprises forming a depression in the thermally conductive copper substrate.

7. The method of claim 1 wherein the substrate comprises a thermally conductive substrate comprised of aluminum, and wherein forming the recess in the substrate comprises forming a depression in the thermally conductive aluminum substrate.

8. The method of claim 1 wherein the substrate comprises a generally circular substrate, and wherein forming the recess in the substrate comprises forming a depression in the generally circular substrate.

9. The method of claim 1 wherein:

the substrate has a first coefficient of thermal expansion; and

the microelectronic die has a second coefficient of thermal expansion at least approximately equal to the first coefficient of thermal expansion.

10. The method of claim 1 wherein the substrate has a first coefficient of thermal expansion that is at least approximately equal to a second coefficient of thermal expansion of a printed circuit board.

11. The method of claim 1 wherein the recess is one of a plurality of recesses, wherein the microelectronic die is one of a plurality of microelectronic dies having first sides and second sides, and wherein the method further comprises:

forming the plurality of recesses in the substrate;

placing the plurality of microelectronic dies in corresponding recesses formed in the substrate with the second sides facing toward the substrate; and

covering the first sides of the microelectronic dies with the dielectric layer after placing the microelectronic dies in the recesses.

12. The method of claim 1, further comprising disposing an adhesive in the recess.

13. The method of claim 1, further comprising depositing a solder ball on a ball-pad in or on the dielectric layer, wherein the ball-pad is electrically coupled to at least one bond-pad of the microelectronic die.

14. A method of packaging a microelectronic device including a microelectronic die having a first side with a plurality of bond-pads and a second side opposite the first side, the method comprising:

placing the microelectronic die in a recess in a substrate with the second side facing toward the substrate, the recess extending into the substrate from a substrate surface;

placing electric couplers on at least some of the bond-pads of the microelectronic die, the individual electric couplers having a first end on the bond-pads of the microelectronic die and a second end opposite the first end;

covering the electric couplers, the first side of the microelectronic die, and the substrate with a dielectric layer, the dielectric layer having a first portion over the microelectronic die and the electric couplers and a second portion in the recess, the first portion of the dielectric layer having a first surface proximate to the substrate surface and a second surface opposite the first surface, the first portion of the dielectric layer having a thickness between the first and second surfaces, the thickness being approximately equal to a height of the electric couplers between the first and second ends; and

forming an array of ball-pads on and/or in the dielectric layer, wherein the ball-pads are electrically coupled to corresponding bond-pads on the die.

15. The method of claim 14, further comprising forming the recess in the substrate.

16. The method of claim 14, further comprising forming a conductive link on the dielectric layer, the conductive link being in direct contact with the electric couplers.

17. The method of claim 14 wherein the substrate comprises a thermally conductive substrate, and wherein placing the microelectronic die in the recess in the substrate comprises placing the microelectronic die in a depression in the thermally conductive substrate.

18. The method of claim 14 wherein the substrate comprises a thermally conductive substrate comprised of copper, and wherein placing the microelectronic die in the recess in the substrate comprises placing the microelectronic die in a depression in the thermally conductive copper substrate.

19. The method of claim 14 wherein the substrate comprises a thermally conductive substrate comprised of aluminum, and wherein placing the microelectronic die in the recess in the substrate comprises placing the microelectronic die in a depression in the thermally conductive aluminum substrate.

20. The method of claim 14 wherein the substrate comprises a generally circular substrate, and wherein placing the microelectronic die in the recess in the substrate comprises placing the microelectronic die in a depression in the generally circular substrate.

21. A method of packaging a semiconductor die, the method comprising:

placing a semiconductor die in a recess of a substrate, the semiconductor die having an integrated circuit, a first side with a bond site electrically coupled to the integrated circuit, and a second side opposite the first side, the recess extending into the substrate from a substrate surface;

placing an electric coupler on the bond site of the semiconductor die, the electric coupler having a first end on the bond site and a second end opposite the first end;

covering the electric coupler, the semiconductor die, and the substrate with a dielectric layer after placing the semiconductor die in the recess, the dielectric layer having a first portion over the semiconductor die and the electric coupler and a second portion in the recess, the first portion of the dielectric layer having a first surface proximate to the substrate surface and a second surface opposite the first surface; and

removing material from the second end of the electric coupler such that the second end of the electric coupler does not project beyond the second surface of the first portion of the dielectric layer.

22. The method of claim 21, further comprising forming a conductive link on the dielectric layer, the conductive link being in direct contact with the electric coupler.