Method for manufacturing semiconductor device

• US 7,655,526 B2
• Filed: 12/12/2006
• Issued: 02/02/2010
• Est. Priority Date: 12/28/2005
• Status: Expired due to Fees

• Current Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Original Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Inventors: Ko, Choul Joo
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US11/638,110
• Publication Number:
  US 20070161249A1
• Time in Patent Office: 1,148 Days
• Field of Search: 438/369, 438/373, 438/514, 438/519, 438/527, 438/275, 438/305, 257/395
• US Class Current: 438/305
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

Disclosed is a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes the steps of forming a gate electrode on a semiconductor substrate, forming a drift area in the semiconductor substrate by implanting a dopant using the gate electrode as a mask, forming a sidewall spacer at sides of the gate electrode, and forming a source/drain area in the semiconductor substrate by implanting a dopant using the gate electrode and the sidewall spacer as a mask.

Claims

1. A method for manufacturing a semiconductor device, the method comprising the steps of:

forming a gate electrode on a semiconductor substrate by patterning a layer containing polysilicon;

forming a drift area in the semiconductor substrate by implanting one or more first dopants using the gate electrode as a mask;

forming a sidewall oxide layer at sides of the gate electrode by oxidizing the gate electrode after forming the drift area;

forming a sidewall spacer at sides of the gate electrode; and

forming a source/drain area in the semiconductor substrate by implanting one or more second dopants using the gate electrode and the sidewall spacer as a mask.

2. The method as claimed in claim 1, wherein the sidewall oxide layer is formed before the sidewall spacer.

3. The method as claimed in claim 1, wherein the step of forming the gate electrode includes the steps of:

depositing a polysilicon layer, an oxide layer, and a nitride layer on the semiconductor substrate; and

sequentially etching the nitride layer, the oxide layer, and the polysilicon layer in a pattern of the gate electrode.

4. The method as claimed in claim 3, comprising dry etching the nitride layer, the oxide layer, and the polysilicon layer.

5. The method as claimed in claim 1, further comprising a step of forming a high-voltage P-well on the semiconductor substrate before forming the gate electrode, wherein forming the drift area comprises implanting an N-dopant.

6. The method as claimed in claim 1, further comprising a step of forming a high-voltage N-well on the semiconductor substrate before forming the gate electrode, wherein forming the drift area comprises implanting a P-dopant.

7. The method as claimed in claim 1, wherein the step of forming the sidewall spacer includes the steps of:

depositing a nitride layer on the semiconductor substrate including the gate electrode; and

blanket etching the nitride layer.

8. The method as claimed in claim 1, further comprising a step of forming a salicide layer on a surface of the gate electrode and the source/drain area after forming the source/drain area.

9. The method as claimed in claim 1, wherein the drift area implant has a maximum depth greater than that of the source/drain area implant.

10. A method for manufacturing a semiconductor device, the method comprising the steps of:

forming a first oxide layer on a semiconductor substrate;

depositing a polysilicon layer, a second oxide layer, and a first nitride layer on the first oxide layer and forming a gate stack by patterning the polysilicon layer, the second oxide layer, and the first nitride layer;

forming a drift area by implanting one or more first dopants into the semiconductor substrate using the gate stack as a mask;

removing the first nitride layer;

depositing a second nitride layer on the semiconductor substrate and forming a sidewall spacer by blanket etching the second oxide layer and the second nitride layer; and

forming a source/drain area in the semiconductor substrate by implanting one or more second dopants using the gate electrode and the sidewall spacer as a mask.

11. The method as claimed in claim 10, further comprising a step of forming a sidewall oxide layer at sides of the gate electrode by oxidizing the gate electrode, after forming the drift area.

12. The method as claimed in claim 10, wherein removing the first nitride layer comprises a wet etching process using a material having a relatively high etching selectivity for etching the first nitride layer relative to the second oxide layer.

13. The method as claimed in claim 12, wherein the material includes H₃PO₄.

14. The method as claimed in claim 13, wherein the material comprises concentrated H₃PO₄.

15. The method as claimed in claim 13, wherein the H₃PO₄ is heated to a temperature of up to about 80°

C. during the etching process.

16. The method as claimed in claim 10, further comprising a step of forming a salicide layer on a surface of the gate electrode and the source/drain area, after forming the source/drain area.

17. The method as claimed in claim 10, wherein the first oxide layer comprises a buffer oxide layer.

18. The method as claimed in claim 10, wherein the first oxide layer comprises a gate oxide layer.

19. The method as claimed in claim 10, wherein blanket etching comprises anisotropic etching or dry plasma etching.