DRAM (dynamic random access memory) cells

• US 7,655,967 B2
• Filed: 07/19/2007
• Issued: 02/02/2010
• Est. Priority Date: 03/22/2006
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Khan, Babar Ali, Cheng, Kangguo
• Primary Examiner(s): MALSAWMA, LALRINFAMKIM HMAR
• Application Number:
  US11/780,022
• Publication Number:
  US 20070257294A1
• Time in Patent Office: 929 Days
• Field of Search: 257/301, 257/E29.346, 257/304, 257/305, 257/E27.09, 257/E27.092, 257/E27.093
• US Class Current: 257/301
• CPC Class Codes: H10B 12/0387 Making the trench

Abstract

A DRAM cell with a self-aligned gradient P-well and a method for forming the same. The DRAM cell includes (a) a semiconductor substrate; (b) an electrically conducting region including a first portion, a second portion, and a third portion; (c) a first doped semiconductor region wrapping around the first portion, but electrically insulated from the first portion by a capacitor dielectric layer; (d) a second doped semiconductor region wrapping around the second portion, but electrically insulated from the second portion by a collar dielectric layer. The second portion is on top of and electrically coupled to the first portion, and the third portion is on top of and electrically coupled to the second portion. The collar dielectric layer is in direct physical contact with the capacitor dielectric layer. When going away from the collar dielectric layer, a doping concentration of the second doped semiconductor region decreases.

Claims

1. A semiconductor structure, comprising:

(a) a semiconductor substrate;

(b) an electrically conducting region in the semiconductor substrate,

wherein the electrically conducting region includes a first portion, a second portion, and a third portion,

wherein the second portion of the electrically conducting region is on top of and electrically coupled to the first portion of the electrically conducting region,

wherein the third portion of the electrically conducting region is on top of and electrically coupled to the second portion of the electrically conducting region,

wherein the second portion of the electrically conducting region is in direct physical contact with a top surface of the first portion of the electrically conducting region, and

wherein the third portion of the electrically conducting region is in direct physical contact with a top surface of the second portion of the electrically conducting region;

(c) a first doped semiconductor region (i) in the semiconductor substrate, (ii) wrapping around side walls and a bottom wall of the first portion of the electrically conducting region, but (iii) electrically insulated from the first portion of the electrically conducting region by both a capacitor dielectric layer and a first portion of a collar dielectric layer; and

(d) a second doped semiconductor region (i) in the semiconductor substrate, (ii) wrapping around side walls of the second portion of the electrically conducting region, but (iii) electrically insulated from the second portion of the electrically conducting region by a second portion of the collar dielectric layer,

wherein the first portion of collar dielectric layer is in direct physical contact with the capacitor dielectric layer, and

wherein when going from an interfacing surface of the collar dielectric layer and the second doped semiconductor region and away from the collar dielectric layer, a doping concentration of the second doped semiconductor region decreases.

2. The semiconductor structure of claim 1,

wherein the first doped semiconductor region comprises dopants having a first doping polarity,

wherein the second doped semiconductor region comprises dopants having a second doping polarity which is opposite to the first doping polarity,

wherein the first portion of the electrically conducting region comprises dopants having the first doping polarity,

wherein the second portion of the electrically conducting region comprises dopants having the first doping polarity, and

wherein the third portion of the electrically conducting region comprises dopants having the first doping polarity.

3. The semiconductor structure of claim 1, further comprising:

a buried strap region in direct physical contact with both the third portion of the electrically conducting region and the second doped semiconductor region, wherein the buried strap region comprises dopants having a first doping polarity; and

a shallow trench isolation in direct physical contact with the buried strap region, the third portion of the electrically conducting region, the second portion of the electrically conducting region, the second portion of the collar dielectric layer, and the second doped semiconductor region.

4. The semiconductor structure of claim 1, wherein the collar dielectric layer consists of the first portion of the collar dielectric layer and the second portion of the collar dielectric layer.

5. The semiconductor structure of claim 1, wherein the first doped semiconductor region is in direct physical contact with an outer surface of the capacitor dielectric layer, wherein the second doped semiconductor region is in direct physical contact with an outer surface of the collar dielectric layer, and wherein the outer surface of the capacitor dielectric layer and the outer surface of the collar dielectric layer are coplanar.

6. The semiconductor structure of claim 1, wherein a thickness of the capacitor dielectric layer is equal to a thickness of the first portion of the collar dielectric layer in a first direction that is perpendicular to the outer surface of the capacitor dielectric layer, and wherein the thickness of the first portion of collar dielectric layer is less than a thickness of the second portion of the collar dielectric layer in the first direction.

7. The semiconductor structure of claim 6, wherein the first portion of collar dielectric layer and the second portion of the collar dielectric layer are integral with each other at a plane that is coplanar with the top surface of the first portion of the electrically conducting region.

8. The semiconductor structure of claim 1, wherein the second doped semiconductor region is in direct physical contact with the first doped semiconductor region.

9. The semiconductor structure of claim 8, wherein the second doped semiconductor region is in direct physical contact with the first doped semiconductor region at a spatial location that is at a same distance from a top surface of the semiconductor substrate as is a distance between the top surface of the first portion of the electrically conducting region and the top surface of the semiconductor substrate.

10. A structure, comprising:

means for forming the semiconductor structure of claim 1, wherein the semiconductor structure further comprises a buried strap region in direct physical contact with both the third portion of the electrically conducting region and the second doped semiconductor region, and wherein the buried strap region comprises dopants having a first polarity; and

an access transistor which includes a first source/drain region and a second source/drain region in the semiconductor substrate, wherein the first source/drain region is in direct physical contact with the buried strap region.

11. A semiconductor fabrication method, said method comprising forming a semiconductor structure, said semiconductor structure comprising:

(a) a semiconductor substrate,

(b) an electrically conducting region in the semiconductor substrate,

wherein the electrically conducting region includes a first portion, a second portion, and a third portion,

wherein the second portion of the electrically conducting region is on top of and electrically coupled to the first portion of the electrically conducting region,

wherein the third portion of the electrically conducting region is on top of and electrically coupled to the second portion of the electrically conducting region,

wherein the second portion of the electrically conducting region is in direct physical contact with a top surface of the first portion of the electrically conducting region, and

wherein the third portion of the electrically conducting region is in direct physical contact with a top surface of the second portion of the electrically conducting region;

(c) a first doped semiconductor region (i) in the semiconductor substrate, (ii) wrapping around side walls and a bottom wall of the first portion of the electrically conducting region, but iii) electrically insulated from the first portion of the electrically conducting region by both a capacitor dielectric layer and a first portion of a collar dielectric layer; and

(d) a second doped semiconductor region (i) in the semiconductor substrate, (ii) wrapping around side walls of the second portion of the electrically conducting region, but (iii) electrically insulated from the second portion of the electrically conducting region by a second portion of the collar dielectric layer,

wherein the first portion of collar dielectric layer is in direct physical contact with the capacitor dielectric layer, and

wherein when going from an interfacing surface of the collar dielectric layer and the second doped semiconductor region and away from the collar dielectric layer, a doping concentration of the second doped semiconductor region decreases.

12. The method of claim 11,

wherein the first doped semiconductor region comprises dopants having a first doping polarity,

wherein the second doped semiconductor region comprises dopants having a second doping polarity which is opposite to the first doping polarity,

wherein the first portion of the electrically conducting region comprises dopants having the first doping polarity,

wherein the second portion of the electrically conducting region comprises dopants having the first doping polarity, and

wherein the third portion of the electrically conducting region comprises dopants having the first doping polarity.

13. The method of claim 11, further comprising:

a buried strap region in direct physical contact with both the third portion of the electrically conducting region and the second doped semiconductor region, wherein the buried strap region comprises dopants having a first doping polarity; and

a shallow trench isolation in direct physical contact with the buried strap region, the third portion of the electrically conducting region, the second portion of the electrically conducting region, the second portion of the collar dielectric layer, and the second doped semiconductor region.

14. The method of claim 11, wherein the collar dielectric layer consists of the first portion of the collar dielectric layer and the second portion of the collar dielectric layer.

15. The method of claim 11, wherein the first doped semiconductor region is in direct physical contact with an outer surface of the capacitor dielectric layer, wherein the second doped semiconductor region is in direct physical contact with an outer surface of the collar dielectric layer, and wherein the outer surface of the capacitor dielectric layer and the outer surface of the collar dielectric layer are coplanar.

16. The method of claim 11, wherein a thickness of the capacitor dielectric layer is equal to a thickness of the first portion of the collar dielectric layer in a first direction that is perpendicular to the outer surface of the capacitor dielectric layer, and wherein the thickness of the first portion of collar dielectric layer is less than a thickness of the second portion of the collar dielectric layer in the first direction.

17. The method of claim 16, wherein the first portion of collar dielectric layer and the second portion of the collar dielectric layer are integral with each other at a plane that is coplanar with the top surface of the first portion of the electrically conducting region.

18. The method of claim 11, wherein the second doped semiconductor region is in direct physical contact with the first doped semiconductor region.

19. The method of claim 18, wherein the second doped semiconductor region is in direct physical contact with the first doped semiconductor region at a spatial location that is at a same distance from a top surface of the semiconductor substrate as is a distance between the top surface of the first portion of the electrically conducting region and the top surface of the semiconductor substrate.