CMOS device with stressed sidewall spacers

• US 7,655,991 B1
• Filed: 09/08/2005
• Issued: 02/02/2010
• Est. Priority Date: 09/08/2005
• Status: Expired due to Fees

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Nayak, Deepak Kumar, Luo, Yuhao
• Primary Examiner(s): Soward; Ida M
• Application Number:
  US11/221,507
• Time in Patent Office: 1,608 Days
• Field of Search: 257/327, 257/336, 257/344, 257/408, 257/900, 257/335, 257/E29.266, 257/E29.267, 257/E29.268, 257/E29.269, 257/E29.278, 257/E29.279
• US Class Current: 257/408
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: Y10S 257/90 MOSFET type gate sidewall insulating spacer

Abstract

Sidewall spacers on the gate of a MOS device are formed from stressed material so as to provide strain in the channel region of the MOS device that enhances carrier mobility. In a particular embodiment, the MOS device is in a CMOS cell that includes a second MOS device. The first MOS device has sidewall spacers having a first (e.g., tensile) type of residual mechanical stress, and the second MOS device has sidewall spacers having a second (e.g., compressive) type of residual mechanical stress. Thus, carrier mobility is enhanced in both the PMOS portion and in the NMOS portion of the CMOS cell.

Claims

1. A semiconductor structure comprising:

a first metal-oxide-semiconductor (“

MOS”

) transistor of a first type having

a first channel region,

a first gate having a first sidewall and a second sidewall,

a first sidewall spacer disposed on the first sidewall; and

a second sidewall spacer disposed on the second sidewall, wherein the first sidewall spacer and the second sidewall spacer are made of a first selectively stressed material having a first type of stress so as to promote carrier mobility in the first channel region;

a second MOS transistor of a second type, the first MOS transistor and the second MOS transistor forming a complementary MOS (“

CMOS”

) cell, the second MOS transistor having

a second channel region;

a second gate having a third sidewall and a fourth sidewall;

a third sidewall spacer disposed on the third sidewall; and

a fourth sidewall spacer disposed on the fourth sidewall, wherein the third sidewall spacer and the fourth sidewall spacer are made of a second selectively stressed material having a second type of stress so as to promote carrier mobility in the second channel region; and

residue of the second selectively stressed material on at least one of the first sidewall spacer and the second sidewall spacer, wherein the residue remains from an etching step forming the third sidewall spacer and the fourth sidewall spacer disposed on the second gate, and wherein one of the first type of stress and the second type of stress comprises a tensile stress and the other of the first type of stress and the second type of stress comprises a compression stress and the width of the first sidewall spacer and the second sidewall spacer are selected to account for the width of the second selectively stressed material on at least one of the first sidewall spacer and the second sidewall spacer.

2. The semiconductor structure of claim 1 wherein the first selectively stressed material comprises silicon nitride having residual tensile stress and the second selectively stressed material comprises silicon nitride having residual compressive stress.

3. The semiconductor structure of claim 1 wherein the first selectively stressed material has residual tensile stress and the second selectively stressed material comprises silicon carbide having residual compressive stress.