Line component and semiconductor circuit using line component

• US 7,656,036 B2
• Filed: 02/13/2004
• Issued: 02/02/2010
• Est. Priority Date: 02/14/2003
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Nakano, Takashi, Tohya, Hirokazu
• Primary Examiner(s): Fahmy; Wael
• Assistant Examiner(s): Armand; Marc
• Application Number:
  US10/545,448
• Publication Number:
  US 20060145309A1
• Time in Patent Office: 2,181 Days
• Field of Search: 257/664, 257/758, 257/759, 257/760, 257/E23.153, 257/E23.144
• US Class Current: 257/758
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A semiconductor circuit in which low impedance characteristics required for a decoupling circuit are ensured up to a band of several hundreds of MHz or above in the situation where digital circuits are rushing into GHz age, and a semiconductor circuit exhibiting low impedance characteristics even in a band of several hundreds of MHz or above. A line element comprising a power supply line and a ground line or a ground plane arranged oppositely through a dielectric, characterized in that a dielectric covering the line element is provided.

Claims

1. A line component in which a power supply interconnection and a ground interconnection or a ground surface are disposed in opposed relation via a first dielectric, wherein a covering which covers the line component is provided, that a second dielectric having a higher permittivity than silicon oxide is provided on the other surface which is not opposed to the ground interconnection or ground surface of the power supply interconnection, and that the second dielectric has a permittivity larger than the permittivity of the covering, wherein the second dielectric comprises LaAlO₃, wherein the permittivity of the second dielectric is six times larger than the permittivity of the covering, and wherein the covering comprises SiO₂.

2. The line component according to claim 1, wherein the line component is formed so as to provide an uneven portion which is substantially perpendicular and/or substantially horizontal to a propagation direction of an electromagnetic wave.

3. The line component according to claim 1, wherein in the line component, sections which are substantially perpendicular and/or substantially horizontal to a propagation direction of an electromagnetic wave are substantially the same.

4. The line component according to claim 1, wherein in a frequency band of an electromagnetic wave generated from a high-frequency source, a characteristic impedance of the line is set so that a peak value of power supply voltage which changes depending on the electromagnetic wave inputted to the line becomes not more than a prescribed value found on the basis of the power supply voltage.

5. A line component which has at least a first dielectric formed in a substantially constant thickness on a semiconductor substrate or a conductor layer and a first conductor formed on the dielectric, wherein a second dielectric having a higher permittivity than silicon oxide is formed on the first conductor, that the first dielectric is formed by specifying the length of the first dielectric relative to the traveling direction of a high-frequency wave traveling in the dielectric to a prescribed length, that a covering of an insulator which covers the line component is provided, and that the second dielectric has a permittivity larger than the permittivity of the covering, wherein the second dielectric comprises LaAlO₃, wherein the permittivity of the second dielectric is six times larger than the permittivity of the covering, and wherein the covering comprises SiO₂.

6. The line component according to claim 5, wherein an uneven portion is formed at least at one of an interface between the semiconductor substrate or the conductor layer or the first dielectric and an interface between the first dielectric and the first conductor.

7. The line component according to claim 5, wherein the first conductor is further formed in film shape and that a second dielectric is formed in film shape between the conductor and the covering.

8. The line component according to claim 5, in which at least one surface of a top surface, a bottom surface and side surfaces of a first conductor is covered with a third dielectric, wherein the line component is covered with a fourth dielectric, that projections and depressions are formed on a surface of the first conductor, and that the third dielectric is formed so as to provide an uneven portion.

9. The line component according to claim 5, wherein the line component has the semiconductor substrate, the conductor layer and the second conductor, that at least one of the semiconductor substrate, the conductor layer and the second conductor is a ground interconnection or is connected to a ground, and that the first conductor is a power supply interconnection.

10. The line component according to claim 8, wherein the third dielectric is formed by specifying the length of the third dielectric relative to the traveling direction of a high-frequency wave traveling in the dielectric to a prescribed length.

11. The line component according to claim 8, wherein the permittivity of the third dielectric provided on at least one surface of a top surface, a bottom surface and side surfaces of the first conductor is higher than the permittivity of the fourth dielectric.

12. The line component according to claim 9, wherein the conductor layer is polycrystalline silicon.