Method for calibrating semiconductor device tester
First Claim
1. A vernier calibration method for calibrating a semiconductor device tester including a plurality of drive channels and a plurality of IO channels for simultaneously testing a plurality of DUTs, the IO channel including a plurality of input channels and a plurality of output channels, the method comprising steps of:
- (a) mounting a second calibration board respectively connecting the plurality of drive channels to the plurality of input channels;
(b) generating a lookup table for the plurality of drive channels by fixing a delay value of a deskew of the plurality of output channels and varying a delay code value of a deskew of the plurality of the drive channels;
(c) generating a lookup table for the plurality of output channels by fixing a delay value of a deskew of the plurality of drive channels and varying a delay code value of a deskew of the plurality of the output channels;
(d) mounting a DUT interface board respectively connecting the plurality of input channels to the plurality of output channels; and
(e) generating a lookup table for the plurality of input channels by fixing the delay value of the deskew of the plurality of output channels and varying a delay code value of a deskew of the plurality of the input channels.
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Abstract
A method for calibrating a semiconductor device tester is disclosed. In accordance with method of the present invention, a timing is calibrated using a programmable delay device and calibration boards so as to remove a timing difference between channels and compensate a linearity of the programmable delay device for an adjustment of a timing by building and using a database of the round trip delay actually generated during the test.
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Citations
11 Claims
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1. A vernier calibration method for calibrating a semiconductor device tester including a plurality of drive channels and a plurality of IO channels for simultaneously testing a plurality of DUTs, the IO channel including a plurality of input channels and a plurality of output channels, the method comprising steps of:
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(a) mounting a second calibration board respectively connecting the plurality of drive channels to the plurality of input channels; (b) generating a lookup table for the plurality of drive channels by fixing a delay value of a deskew of the plurality of output channels and varying a delay code value of a deskew of the plurality of the drive channels; (c) generating a lookup table for the plurality of output channels by fixing a delay value of a deskew of the plurality of drive channels and varying a delay code value of a deskew of the plurality of the output channels; (d) mounting a DUT interface board respectively connecting the plurality of input channels to the plurality of output channels; and (e) generating a lookup table for the plurality of input channels by fixing the delay value of the deskew of the plurality of output channels and varying a delay code value of a deskew of the plurality of the input channels. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A calibration method of a semiconductor device tester including a plurality of drive channels and a plurality of IO channels for simultaneously testing a plurality of DUTs, the IO channel including a plurality of input channels and a plurality of output channels, the method comprising steps of:
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(a) aligning a plurality of output signals of the plurality of output channels with reference to a drive signal of one of the plurality of drive channels using a first calibration board wherein the first calibration board connects the one of the plurality of drive channels to the plurality of the output channels; (b) aligning a plurality of drive signals of the plurality of drive channels with reference to the plurality of aligned output signals using a second calibration board wherein second calibration board respectively connects the plurality of drive channels to the plurality of output channels; (c) aligning a plurality of input signals with reference to the plurality of aligned output signals using a DUT interface board wherein the DUT interface board respectively connects the plurality of input channels to the plurality of output channels; (d) generating a lookup table for the plurality of drive channels by fixing a delay value of a deskew of the plurality of output channels and varying a delay code value of a deskew of the plurality of the drive channels after mounting the second calibration board; (e) generating a lookup table for the plurality of output channels by fixing a delay value of a deskew of the plurality of drive channels and varying a delay code value of a deskew of the plurality of the output channels; and (f) generating a lookup table for the plurality of input channels by fixing the delay value of the deskew of the plurality of output channels and varying a delay code value of a deskew of the plurality of the input channels after mounting the DUT interface board.
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Specification