Testing method using a scalable parametric measurement macro

• US 7,656,182 B2
• Filed: 03/21/2007
• Issued: 02/02/2010
• Est. Priority Date: 03/21/2007
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: McMahon, Robert J., Goss, John R., Habib, Nazmul, Bickford, Jeanne P.
• Primary Examiner(s): Nguyen; Ha Tran T
• Assistant Examiner(s): CAMPBELL, SHAUN M
• Application Number:
  US11/689,150
• Publication Number:
  US 20080231307A1
• Time in Patent Office: 1,049 Days
• Field of Search: 324/765
• US Class Current: 324/762.06
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2894 Aspects of quality control [QC] G01R31/31718 takes precedence; program control for QC G05B19/41875
• CPC Class Codes: G01R 31/30 Marginal testing, e.g. by varying supply voltage testing computers during standby operation or idle time G06F11/22

Abstract

Disclosed are testing method embodiments in which, during post-manufacture testing, parametric measurements are taken from on-chip parametric measurement elements and used to optimize manufacturing in-line parametric control learning and/or to optimize product screening processes. Specifically, these post-manufacture parametric measurements can be used to disposition chips without shipping out non-conforming products, without discarding conforming products, and without requiring high cost functional tests. They can also be used to identify yield sensitivities to parametric variations from design and to provide feedback for manufacturing line improvements based on the yield sensitivities. Additionally, a historical database regarding the key parameters that are monitored at both the fabrication and post-fabrication levels can be used to predict future yield and, thereby, to preemptively improve the manufacturing line and/or also to update supply chain forecasts.

Claims

1. A testing method for chips, said method comprising:

testing all chips from a lot after manufacture,

wherein each chip comprises a parametric performance monitoring system on said chip, wherein said parametric performance monitoring system comprises at least one on-chip parametric measurement macro comprising a plurality of individually selectable test circuits to perform different types of tests,

wherein each of said individually selectable test circuits comprises a device under test,

wherein at least two devices under test comprise different types of devices under test, and

wherein, for each chip, said testing comprises taking, by said parametric performance monitoring system on said chip, parametric measurements from said at least one on-chip parametric measurement macro, said parametric measurements comprising actual measured values for at least one parameter for each device under test and said at least one parameter comprising one of on current (Ion) and threshold voltage (Vt);

determining yield loss based on results of said testing of said all of said chips; and

correlating said yield loss with said parametric measurements to identify yield sensitivity to variations in said parametric measurements.

2. The method of claim 1, wherein said testing comprises at least one of wafer level testing, module level testing, burn-in level testing and application level testing.

3. The method of claim 2, further comprising:

identifying faulty chips at any one of said wafer level testing, said module level testing, said burn-in level testing and said application level testing, wherein any chip, having a predetermined number of said parametric measurements that do not meet predetermined pass/fail criteria, is considered faulty, said predetermined number being greater than one; and

discarding said faulty chips.

4. The method of claim 1, wherein said individually selectable test circuits are each coupled to a control block and to a power supply and wherein said different types of devices under test comprise at least any two of an array of field effect transistors, a resistor, a capacitor, and an inductor.

5. The method of claim 1, further comprising:

analyzing manufacturing processes and tools to identify at least one of a tool and a process which causes said variations in said parametric measurements and, thereby, affects yield; and

improving upon said at least one of said tool and said process.

6. The method of claim 1, further comprising, before said testing of said chips to determine said yield loss, performing in-line testing by taking additional parametric measurements from scribe line measurement structures in scribe lines of said wafer.

7. The method of claim 6, wherein said scribe line measurement structures comprise the same structures as said parametric measurement macro such that said scribe line measurement structures similarly comprise a plurality of individually selectable test circuits each coupled to a control block and to a power supply and each configured to determine at least one of on current (Ion) and threshold voltage (Vt).

8. The method of claim 6, further comprising:

determining correlations between said additional parametric measurements taken from said scribe line measurement structures during said in-line testing and said parametric measurements taken from said parametric measurement macro after said in-line testing; and

using said correlations following subsequent in-line testing of subsequently manufactured chips on subsequently manufactured wafers to at least one of making a yield prediction and customize subsequent testing after manufacture for said subsequently manufactured chips.

9. The method of claim 8, further comprising, based on said yield prediction, one of pre-emptively making manufacturing line improvement and updating supply-chain forecasts.

10. A program storage device readable by computer and tangibly embodying a program of instructions executable by said computer to perform a testing method for chips, said method comprising:

testing all chips from a lot after manufacture,

wherein each chip comprises a parametric performance monitoring system on said chip,

wherein said parametric performance monitoring system comprises at least one on-chip parametric measurement macro comprising a plurality of individually selectable test circuits to perform different types of tests,

wherein each of said individually selectable test circuits comprises a device under test,

wherein at least two devices under test comprise different types of devices under test, and

wherein, for each chip, said testing comprises taking, by said parametric performance monitoring system on said chip, parametric measurements from said at least one on-chip parametric measurement macro, said parametric measurements comprising actual measured values for at least one parameter for each device under test and said at least one parameter comprising one of on current (Ion) and threshold voltage (Vt);

determining yield loss based on results of said testing of said all of said chips; and

correlating said yield loss with said parametric measurements to identify yield sensitivity to variations in said parametric measurements.

11. The program storage device of claim 10, wherein said testing comprises at least one of wafer level testing, module level testing, burn-in level testing and application level testing.

12. The program storage device of claim 10, wherein said method further comprises:

identifying faulty chips at any one of said wafer level testing, said module level testing, said burn-in level testing and said application level testing, wherein any chip, having a predetermined number of said parametric measurements that do not meet predetermined pass/fail criteria, is considered faulty, said predetermined number being greater than one; and

discarding said faulty chips.

13. The program storage device of claim 10, wherein said individually selectable test circuits are each coupled to a control block and to a power supply and wherein said different types of devices under test comprise at least any two of an array of field effect transistors, a resistor, a capacitor, and an inductor.

14. The program storage device of claim 10, wherein said method further comprises:

analyzing manufacturing processes and tools to identify at least one of a tool and a process which causes said variations in said parametric measurements and, thereby, affects yield; and

improving upon said at least one of said tool and said process.

15. The program storage device of claim 10, wherein said method further comprises, before said testing of said chips to determine said yield loss, performing in-line testing by taking additional parametric measurements from scribe line measurement structures in scribe lines of said wafer.

16. The program storage device of claim 15, wherein said scribe line measurement structures comprise the same structures as said parametric measurement macro such that said scribe line measurement structures similarly comprise a plurality of individually selectable test circuits each coupled to a control block and to a power supply and each configured to determine at least one of on current (Ion) and threshold voltage (Vt).

17. The program storage device of claim 15, wherein said method further comprises:

determining correlations between said additional parametric measurements taken from said scribe line measurement structures during said in-line testing and said parametric measurements taken from said parametric measurement macro after said in-line testing; and

using said correlations following subsequent in-line testing of subsequently manufactured chips on subsequently manufactured wafers to at least one of making a yield prediction and customize subsequent testing after manufacture of said subsequently manufactured chips.

18. The program storage device of claim 17, based on said yield prediction, one of pre-emptively making a manufacturing line improvement and updating supply-chain forecasts.

19. A testing method for chips manufactured with on-chip parametric measurement macros, said method comprising:

testing all chips from a lot after manufacture,

wherein each chip comprises a parametric performance monitoring system on said chip,

wherein said parametric performance monitoring system comprises at least one on-chip parametric measurement macro comprising a plurality of individually selectable test circuits to perform different types of tests,

wherein each of said individually selectable test circuits comprises a device under test,

wherein at least two devices under test comprise different types of devices under test, and

wherein, for each chip, said testing comprises taking, by said parametric performance monitoring system on said chip, parametric measurements from said at least one of said on-chip parametric measurement macro, said parametric measurements comprising actual measured values for at least one parameter for each device under test and said at least one parameter comprising one of on current (Ion) and threshold voltage (Vt);

identifying faulty chips, wherein any chip, having a predetermined number of said parametric measurements that do not meet predetermined pass/fail criteria, is considered faulty; and

discarding said faulty chips from said lot.

20. The method of claim 19, wherein said testing comprises at least one of wafer level testing, module level testing, burn-in level testing, and application level testing and wherein said different types of devices under test comprise at least any two of an array of field effect transistors, a resistor, a capacitor, and an inductor.

21. The method of claim 19, further comprising:

determining yield loss based on results of said testing; and

correlating said yield loss with said parametric measurements to identify yield sensitivity to variations in said parametric measurements.

22. The method of claim 19, further comprising determining said predetermined pass/fail criterion.

23. The method of claim 19, further comprising, performing in-line testing on a sample of said chips selected from a sample of wafers in said lot, wherein said in-line testing comprises taking additional parametric measurements from scribe line measurement structures in wafer scribe lines.

24. The method of claim 23, further comprising, after said performing of said in-line testing, performing said testing after manufacture on all of said chips on all of said wafers in said lot.

25. The method of claim 23, further comprising, after said performing of said in-line testing:

identifying faulty wafers;

discarding any of said faulty wafers; and

performing said testing after manufacture on all remaining wafers in said lot.

26. The method of claim 23, wherein said scribe line measurement structures comprise the same structures as said parametric measurement macros such that said scribe line measurement structures similarly comprise a plurality of individually selectable test circuits each coupled to a control block and to a power supply and each configured to determine at least one of on current (Ion) and threshold voltage (Vt).

34. The method of claim 19, wherein said individually selectable test circuits are each coupled to a control block and to a power supply and wherein said different types of devices under test comprise at least any two of an array of p-type field effect transistors (PFETS), an array of n-type field effect transistors (NFETS), a resistor, a capacitor, and an inductor.

27. A program storage device readable by computer and tangibly embodying a program of instructions executable by said computer to perform a testing method for chips manufactured with on-chip parametric measurement macros, said method comprising:

testing all chips from a lot after manufacture,

wherein each chip comprises a parametric performance monitoring system on said chip,

wherein said parametric performance monitoring system comprises at least one on-chip parametric measurement macro comprising a plurality of individually selectable test circuits to perform different types of tests,

wherein each of said individually selectable test circuits comprises a device under test,

wherein at least two devices under test comprise different types of devices under test, and

wherein, for each chip, said testing comprises taking, by said parametric performance monitoring system on said chip, parametric measurements from said at least one of said on-chip parametric measurement macro, said parametric measurements comprising actual measured values for at least one parameter for each device under test and said at least one parameter comprising one of on current (Ion) and threshold voltage (Vt);

identifying faulty chips, wherein any chip, having a predetermined number of said parametric measurements that do not meet predetermined pass/fail criteria, is considered faulty; and

discarding said faulty chips from said lot.

28. The program storage device of claim 27, wherein said testing comprises at least one of wafer level testing, module level testing, a burn-in level testing, and application level testing.

29. The program storage device of claim 27, further comprising:

determining yield loss based on results of said testing; and

correlating said yield loss with said parametric measurements to identify yield sensitivity to variations in said parametric measurements.

30. The program storage device of claim 27, wherein said method further comprises, performing in-line testing on a sample of said chips selected from a sample of wafers in said lot, wherein said in-line testing comprises taking additional parametric measurements from scribe line measurement structures in wafer scribe lines.

31. The program storage device of claim 30, wherein said method further comprises, after said performing of said in-line testing, performing said testing after manufacture on all of said chips on all of said wafers in said lot.

32. The program storage device of claim 30, wherein said method further comprises, after said performing of said in-line testing:

identifying faulty wafers;

discarding any of said faulty wafers; and

performing said testing after manufacture on all remaining wafers in said lot.

33. The program storage device of claim 30, wherein said scribe line measurement structures comprise the same structures as said parametric measurement macros such that said scribe line measurement structures similarly comprise a plurality of individually selectable test circuits each coupled to a control block and to a power supply and each configured to determine at least one of on current (Ion) and threshold voltage (Vt).