Multiple-phase, differential sampling and steering

• US 7,656,200 B2
• Filed: 06/30/2008
• Issued: 02/02/2010
• Est. Priority Date: 06/30/2008
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hyvonen, Sami
• Primary Examiner(s): Wells; Kenneth B.
• Application Number:
  US12/164,951
• Publication Number:
  US 20090322403A1
• Time in Patent Office: 582 Days
• Field of Search: 327/91, 327/356, 327/357, 327/359
• US Class Current: 327/91
• CPC Class Codes: G06G 7/18 for integration or differentiation; for forming integrals G06G7/19 takes precedence

Abstract

Methods and systems to controllably steer multiple phases of a differential signal, including to generate a differential current in response to a differential voltage, to controllably steer the differential current between multiple output circuits in response to corresponding control signals, which may be out of phase with respect to one another, and to generate multiple corresponding outputs corresponding to the multiple steered phases of the current. A differential input circuit and a current steering circuit may be common to multiple output circuits, and a common offset compensation may be provided to compensate for a substantial portion of offset associated with the multiple outputs.

Claims

1. A system, comprising:

a differential input circuit including first and second differential output nodes;

first and second differential output circuits each including first and second differential input nodes; and

a differential steering circuit, including first and second control nodes to receive first and second control signals, to steer a differential signal from the first and second differential output nodes of the differential input circuit to the first and second differential input nodes of the first differential output circuit in response to the first control signal and to the first and second differential input nodes of the second differential output circuit in response to the second control signal.

2. The system of claim 1, wherein the differential steering circuit includes a differential steering switch to selectively steer the differential signal to a selected one of the first and second differential output circuits in response to the first and second control signals.

3. The system of claim 1, wherein the differential steering circuit includes:

a first differentially controlled steering circuit coupled between the first differential output node of the differential input circuit and the first differential input nodes of the first and second differential output circuits, and coupled to the first and second control nodes; and

a second differentially controlled steering circuit coupled between the second differential output node of the differential input circuit and the second differential input nodes of the first and second differential output circuits, and coupled to the first and second control nodes.

4. The system of claim 1, wherein the differential steering circuit includes:

a first differential sample circuit coupled between the first and second differential output nodes of the differential input circuit and the first and second differential input nodes of the first differential output circuit, and coupled to the first control node; and

a second differential sample circuit coupled between the first and second differential output nodes of the differential input circuit and the first and second differential input nodes of the second differential output circuit, and coupled to the second control node.

5. The system of claim 1, wherein the differential steering circuit includes:

a first sample circuit coupled between the first differential output node of the differential input circuit and the first differential input node of the first differential output circuit, and coupled to the first control node;

a second sample circuit coupled between the second differential output node of the differential input circuit and the second differential input node of the first differential output circuit, and coupled to the second control node;

a third sample circuit coupled between the first differential output node of the differential input circuit and the first differential input node of the second differential output circuit, and coupled to the first control node; and

a fourth sample circuit coupled between the second differential output node of the differential input circuit and the second differential input node of the second differential output circuit, and coupled to the second control node.

6. The system of claim 5, wherein the first output circuit includes:

a first transistor device coupled between the first differential input node of the first differential output circuit and a first differential output node of the first differential output circuit;

a second transistor device coupled between the second differential input node of the first differential output circuit and a second differential output node of the first differential output circuit;

a third transistor device coupled between the first differential output node of the first differential output circuit and a ground terminal;

a fourth transistor device coupled between the second differential output node of the first differential output circuit and a ground terminal; and

cross-couple circuitry to couple the first differential output node of the first differential output circuit to control terminals of the second and fourth transistor devices, and to couple the second differential output node of the first differential output circuit to control terminals of the first and third transistor devices.

7. The system of claim 6, wherein the first differential output circuit further includes reset circuitry to reset a state of the first differential output circuit in response to a reset signal.

8. The system of claim 7, wherein the reset circuitry includes reset circuitry coupled between each of the first and second differential output nodes of the first differential output circuit and a reset node, and coupled to a reset control node.

9. The system of claim 8, wherein the reset circuitry further includes reset circuitry coupled between each of the first and second differential input nodes of the first differential output circuit and the reset node, and coupled to the reset control node.

10. The system of claim 8, wherein the reset circuitry further includes reset circuitry coupled between the first and second differential input nodes of the first differential output circuit, and coupled to the reset control node.

11. The system of claim 1, wherein the differential input circuit includes:

a bias current source to provide a relatively fixed current; and

first and second transistor devices, each including a control terminal to receive a differential input signal, a first conduction terminal coupled to the bias current source, and a second conduction terminal coupled to a corresponding one of the first and second output nodes of the differential input circuit.

12. The system of claim 1, further comprising one or more additional differential output circuits, each including corresponding first and second differential input nodes, wherein the differential steering circuit is configured to selectively steer the differential signal from the first and second differential output nodes of the differential input circuit to corresponding first and second differential input nodes of one or more of the first, second, and one or more additional differential output circuits in response to the first, second, and one or more corresponding additional control signals.

13. The system of claim 1, further comprising:

a differential amplifier to provide a differential input signal to the differential input circuit;

a digital signal processor to determine offset values corresponding to each of the first and second differential output circuits and to generate a common offset compensation from a combination of the offset values corresponding to the first and second differential output circuits; and

a digital to analog converter to provide the common offset compensation to the differential amplifier;

wherein the differential amplifier is configured to apply the common offset compensation to the differential input signal.

14. A method, comprising:

generating a differential current in response to a differential input voltage, wherein the differential current includes first and second portions that are substantially out of phase with one another;

controllably steering the first and second portions of the differential current to a first differential output circuit in response to a first control signal and to a second differential output circuit in response to a second control signal;

generating first and second differential output voltages at the corresponding first and second differential output circuits, each of the first and second differential output voltages including first and second portions that are substantially out of phase with one another.

15. The method of claim 14, wherein the generating the differential current includes steering a relatively fixed current between first and second differential nodes in response to the differential input voltage.

16. The method of claim 14, wherein the controllably steering includes switching the differential current between the first and second differential output circuits in response to the control signals.

17. The method of claim 14, wherein the controllably steering includes differentially sampling the differential current in response to the first control signal and differentially sampling the differential current in response to the second control signal.

18. The method of claim 14, further comprising:

determining offsets corresponding to each of the first and second differential output voltages;

generating a common offset compensation from a combination of the offsets of the first and second differential output voltages; and

applying the common offset compensation to the differential input voltage.

19. A system, comprising:

a differential input circuit to apportion a relatively fixed current amongst first and second differential output nodes in response to a differential input voltage;

first and second differential output circuits each including first and second differential input nodes; and

a differential sample and steer circuit to sample the differential current at the first and second differential output nodes of the differential input circuit, and to steer corresponding current samples to the first and second differential input nodes of the first differential output circuit in response to a first control signal, and to the first and second differential input nodes of the second differential output circuit in response to a second control signal.

20. The system of claim 19, further comprising:

a differential amplifier to provide the differential input voltage to the differential input circuit;

a digital signal processor to determine an offset value corresponding to each of the first and second differential output circuits and to determine an offset compensation from a combination of the offset values corresponding to the first and second differential output circuits; and

a digital to analog converter to provide the offset compensation to the differential amplifier;

wherein the differential amplifier is configured to apply the offset compensation to the differential input voltage.