Semiconductor integrated circuit
First Claim
1. A semiconductor integrated circuit operating on multiple supply potentials including a first supply potential and a second supply potential that is higher than the first supply potential, comprising:
- a potential-lowering circuit operating on the second supply potential and including an N-channel MOS transistor whose gate and drain receive the second supply potential and that outputs a third supply potential from a source thereof, the third supply potential being lower than the second supply potential;
a judging circuit operating on the third supply potential outputted from the potential-lowering circuit and judging whether the first supply potential is high-level or low-level;
a buffer circuit outputting a control signal showing whether the first supply potential is fed based on judgment outputted from the judging circuit,the judging circuit including;
a first inverter that receives and inverts the first supply potential; and
multiple P-channel MOS transistors whose source-drain paths are series-connected between the second supply potential and an output node of the first inverter, andthe judging circuit includes a second inverter that inverts a signal outputted from the first inverter, a signal outputted from the second inverter is fed to a gate of a first P-channel MOS transistor out of the multiple P-channel MOS transistors, and a gate of another P-channel MOS transistor out of the multiple P-channel MOS transistors is connected to the first supply potential.
2 Assignments
0 Petitions
Accused Products
Abstract
A semiconductor integrated circuit that operates on multiple supply potentials including a first potential and a second potential that is higher than the first potential. The semiconductor integrated circuit includes a potential-lowering circuit operating on the second supply potential and including an N-channel MOS transistor that lowers the second supply potential applied to a gate thereof to output a lowered potential from a source thereof, a judging circuit operating on the potential outputted from the potential-lowering circuit and judging whether the first supply potential is high-level or low-level, and a buffer circuit outputting a control signal showing whether the first supply potential is fed based on judgment outputted from the judging circuit.
11 Citations
7 Claims
-
1. A semiconductor integrated circuit operating on multiple supply potentials including a first supply potential and a second supply potential that is higher than the first supply potential, comprising:
-
a potential-lowering circuit operating on the second supply potential and including an N-channel MOS transistor whose gate and drain receive the second supply potential and that outputs a third supply potential from a source thereof, the third supply potential being lower than the second supply potential; a judging circuit operating on the third supply potential outputted from the potential-lowering circuit and judging whether the first supply potential is high-level or low-level; a buffer circuit outputting a control signal showing whether the first supply potential is fed based on judgment outputted from the judging circuit, the judging circuit including; a first inverter that receives and inverts the first supply potential; and multiple P-channel MOS transistors whose source-drain paths are series-connected between the second supply potential and an output node of the first inverter, and the judging circuit includes a second inverter that inverts a signal outputted from the first inverter, a signal outputted from the second inverter is fed to a gate of a first P-channel MOS transistor out of the multiple P-channel MOS transistors, and a gate of another P-channel MOS transistor out of the multiple P-channel MOS transistors is connected to the first supply potential. - View Dependent Claims (2, 3, 4, 6)
-
-
5. A semiconductor integrated circuit operating on multiple supply potentials including a first supply potential and a second supply potential that is higher than the first supply potential, comprising:
-
a potential-lowering circuit operating on the second supply potential and including an N-channel MOS transistor whose gate and drain receive the second supply potential and that outputs a third supply potential from a source thereof;
the third supply potential being lower than the second supply potential;a judging circuit operating on the third supply potential outputted from the potential-lowering circuit and judging whether the first supply potential is high-level or low-level; a buffer circuit outputting a control signal showing whether the first supply potential is fed based on judgment outputted from the judging circuit, the judging circuit including; a first inverter that receives and inverts the first supply potential; and multiple P-channel MOS transistors whose source-drain paths are series-connected between the second supply potential and an output node of the first inverter, the judging circuit includes a second inverter that inverts a signal outputted from the first inverter, a signal outputted from the second inverter is fed to a gate of a first P-channel MOS transistor out of the multiple P-channel MOS transistors, and a gate of another P-channel MOS transistor out of the multiple P-channel MOS transistors is connected to a ground potential, the first inverter includes multiple P-channel MOS transistors whose drain-source paths are series-connected and whose gates are applied with the first supply potential, and the second inverter includes multiple P-channel MOS transistors whose source-drain paths are series-connected and whose gates are applied with signals outputted from the first inverter.
-
-
7. A semiconductor integrated circuit operating on multiple supply potentials including a first supply potential and a second supply potential that is higher than the first supply potential, comprising:
-
a potential-lowering circuit operating on the second supply potential and including an N-channel MOS transistor whose gate and drain receive the second supply potential and that outputs a third supply potential from a source thereof, the third supply potential being lower than the second supply potential; a judging circuit operating on the third supply potential outputted from the potential-lowering circuit and judging whether the first supply potential is high-level or low-level; a buffer circuit outputting a control signal showing whether the first supply potential is fed based on judgment outputted from the judging circuit; an internal circuit that operates on the first supply potential; a first level-shifter and a second level-shifter that shift a potential of a signal outputted from the internal circuit; an output driver including a P-channel MOS transistor and an N-channel MOS transistor that are series-connected to generate an output signal based on a signal outputted from the first level-shifter and the second level-shifter, respectively, when the second supply potential is fed; and a switching circuit that fixes a gate potential of the P-channel MOS transistor at a high level and a gate potential of the N-channel MOS transistor at a low level based on the control signal outputted from the buffer circuit, the judging circuit including; a first inverter that receives and inverts the first supply potential; and multiple P-channel MOS transistors whose source-drain paths are series-connected between the second supply potential and an output node of the first inverter.
-
Specification