Discrete clock generator and timing/frequency reference

• US 7,656,244 B2
• Filed: 02/22/2008
• Issued: 02/02/2010
• Est. Priority Date: 03/22/2004
• Status: Expired due to Fees

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Mobius Microsystems, Inc. (Renesas Electronics Corporation)
• Inventors: McCorquodale, Michael Shannon, Pernia, Scott Michael, Kubba, Sundus, O'Day, Justin, Carichner, Gordon
• Primary Examiner(s): MIS, DAVID C
• Application Number:
  US12/036,165
• Publication Number:
  US 20080150645A1
• Time in Patent Office: 711 Days
• Field of Search: 331/1.A, 331/2, 331/8, 331/10, 331/11, 331 16- 18, 331/25, 331/36.C, 331/36.L, 331/57, 331/117.R, 331/117.FE, 331/117.D, 331/173, 331/175, 331/177.R, 331/177.V, 331/179, 331/DIG.2
• US Class Current: 331/179
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: H03B 2201/025 the means being an electronic switch for switching in or out oscillator elements
• CPC Class Codes: H03B 5/06 Modifications of generator to ensure starting of oscillations
• CPC Class Codes: H03B 5/1212 the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
• CPC Class Codes: H03B 5/1215 the current source or degeneration circuit being in common to both transistors of the pair, e.g. a cross-coupled long-tailed pair
• CPC Class Codes: H03B 5/1221 the amplifier comprising multiple amplification stages connected in cascade
• CPC Class Codes: H03B 5/124 the means comprising a voltage dependent capacitance
• CPC Class Codes: H03J 1/0008 using a central processing unit, e.g. a microprocessor digital tuning in general H03J5/0245
• CPC Class Codes: H03J 2200/10 Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03L 1/00 Stabilisation of generator output against variations of physical values, e.g. power supply
• CPC Class Codes: H03L 1/02 against variations of temperature only
• CPC Class Codes: H03L 1/022 by indirect stabilisation, i.e. by generating an electrical correction signal which is a function of the temperature H03L1/021 takes precedence
• CPC Class Codes: H03L 1/025 and a memory for digitally storing correction values
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 3/00 Starting of generators
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/183 a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number H03L7/1806 takes precedence

Abstract

In various embodiments, the invention provides a discrete clock generator and/or a timing and frequency reference using an LC-oscillator topology, having a frequency controller to control and provide a stable resonant frequency, which may then be provided to other, second circuitry such as a processor or controller. Frequency stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages. The controlled reactance modules may include fixed or variable capacitances or inductances, and may be binary weighted. Arrays of resistive modules are also provided, to generate one or more control voltages.

Claims

1. An integrated circuit comprising:

a reference oscillator comprising an inductor and a capacitor, the reference oscillator adapted to provide a first reference signal having a first frequency;

a plurality of controlled reactance modules coupled to the reference oscillator, each reactance module of the plurality of reactance modules adapted to provide a selected reactance in response to a control voltage to maintain the first frequency substantially constant in a first operating mode; and

an output circuit adapted to provide an output interface for signal communication.

2. The integrated circuit of claim 1, further comprising:

a voltage controller coupled to the plurality of controlled reactance modules, the voltage controller adapted to provide the control voltage.

3. The integrated circuit of claim 1, further comprising:

a control circuit coupled to the plurality of controlled reactance modules, the control circuit adapted to provide a time-dependent switching of the plurality of controlled reactance modules, in a second operating mode, to provide a spread-spectrum first reference signal having a plurality of different first frequencies over time.

4. The integrated circuit of claim 1, further comprising:

a divider circuit coupled to the reference oscillator, the divider circuit adapted to provide a second reference signal at a second frequency.

5. The integrated circuit of claim 4, further comprising:

a locking circuit coupled to the divider circuit and adapted to lock to the second reference signal and provide a third reference signal having a third frequency, the third frequency determined from the second frequency and a divide ratio of the locking circuit.

6. The integrated circuit of claim 5, further comprising:

a control circuit coupled to the locking circuit, the control circuit adapted to provide a time-dependent variance of the divide ratio to provide a spread-spectrum third reference signal having a plurality of different third frequencies over time.

7. The integrated circuit of claim 4, wherein the output circuit is configurable for selection of a signal type of a plurality of signal types of the second reference signal, the plurality of signal types comprising at least one of the following signal types:

differential, single-ended, full voltage rail-to-full voltage rail, or fractional voltage rail-to-fractional voltage rail.

8. The integrated circuit of claim 4, further comprising:

a plurality of locking circuits coupled to the divider circuit, the plurality of locking circuits adapted to lock to the second reference signal and provide a corresponding plurality of third reference signals having a plurality of corresponding third frequencies, each third frequency of the plurality of corresponding third frequencies determined from the second frequency and a divide ratio of the corresponding locking circuit of the plurality of locking circuits.

9. The integrated circuit of claim 8, wherein each locking circuit of the plurality of locking circuits is at least one of the following locking circuits:

a phase-locked loop, a delay-locked loop, or an injection locking circuit.

10. The integrated circuit of claim 8, wherein each locking circuit of the plurality of locking circuits is configurable for selection of the divide ratio.

11. The integrated circuit of claim 8, further comprising:

a plurality of output circuits adapted to provide a corresponding plurality of output interfaces for signal communication; and

first switching circuitry coupled to the plurality of locking circuits and to the plurality of output circuits, the first switching circuitry adapted to selectively switch a selected, third reference signal of the plurality of third reference signals to a selected output circuit of the plurality of output circuits.

12. The integrated circuit of claim 11, further comprising:

control circuitry coupled to the plurality of output circuits, the control circuitry adapted to provide a control signal to a selected output circuit of the plurality of output circuits for selection of a signal type of a plurality of signal types of a corresponding third reference signal, the plurality of signal types comprising at least one of the following signal types;

differential, single-ended, full voltage rail-to-full voltage rail, or fractional voltage rail-to-fractional voltage rail.

13. The integrated circuit of claim 11, further comprising:

control circuitry coupled to the first switching circuitry, the control circuitry adapted to provide a control signal to the first switching circuitry to switch the selected, third reference signal to the selected output circuit.

14. The integrated circuit of claim 11, further comprising:

a coefficient register coupled to the first switching circuitry, the coefficient register adapted to provide a first control coefficient of a first plurality of control coefficients to the first switching circuitry to switch the selected, third reference signal to the selected output circuit.

15. The integrated circuit of claim 14, wherein the coefficient register is further coupled to the plurality of controlled reactance modules, the coefficient register adapted to store a second plurality of coefficients and to provide a corresponding coefficient of the second plurality of coefficients to control a switching of a corresponding controlled reactance module to the oscillator.

16. The integrated circuit of claim 15, further comprising:

a voltage controller coupled to the plurality of controlled reactance modules, the voltage controller adapted to provide the control voltage; and

wherein the plurality of controlled reactance modules further comprise;

a second plurality of switches coupled to the coefficient register; and

a plurality of variable capacitors correspondingly coupled to the second plurality of switches and to the voltage controller, the plurality of variable capacitors adapted to provide a selected capacitance in response to the control voltage.

17. The integrated circuit of claim 16, wherein the plurality of controlled reactance modules further comprise:

a plurality of fixed capacitors correspondingly coupled to the second plurality of switches, the plurality of fixed capacitors adapted to provide a selected capacitance in response to a corresponding coefficient.

18. The integrated circuit of claim 15, wherein the second plurality of coefficients is determined post-fabrication by calibration to an external signal providing a reference frequency.

19. The integrated circuit of claim 15, further comprising:

a user interface coupled to the coefficient register, the user interface adapted to provide a coefficient of the first plurality of coefficients or second plurality of coefficients to the coefficient register in response to user input.

20. The integrated circuit of claim 11, wherein the first switching circuitry comprises a plurality of multiplexers and demultiplexers, or a plurality of pass-transistors, or a cross-bar switch.

21. The integrated circuit of claim 1, wherein the first frequency is mask programmable through selection of a size of the inductor, or through selection of a plurality of connections of the plurality of controlled reactance modules, or through selection of a plurality of sizes of the plurality of controlled reactance modules.

22. The integrated circuit of claim 1, wherein the first frequency is configurable post-fabrication through selection of a plurality of connections of the plurality of controlled reactance modules.

23. The integrated circuit of claim 1, wherein the oscillator has at least one configuration of the following configurations:

a double-balanced, differential LC configuration;

a differential n-MOS cross-coupled topology;

a differential p-MOS cross-coupled topology;

a single-ended Colpitts LC configuration;

a single-ended Hartley LC configuration;

a differential, common base Colpitts LC configuration;

a differential, common collector Colpitts LC configuration;

a differential, common base Hartley LC configuration;

a differential, common collector Hartley LC configuration;

a single-ended Pierce LC oscillator, or a quadrature LC oscillator configuration.

24. The integrated circuit of claim 1, further comprising a variable current source, the variable current source adapted to provide a corresponding current in response to ambient or operating temperature.

25. An integrated circuit comprising:

a reference harmonic oscillator comprising an inductor and a capacitor, the harmonic oscillator adapted to provide a first reference signal having a first frequency;

a first plurality of controlled reactance modules coupled to the reference harmonic oscillator, each reactance module of the first plurality of reactance modules adapted to provide a selected reactance in response to a control voltage to maintain the first frequency substantially constant in a first operating mode;

a first coefficient register adapted to store a first plurality of switching coefficients;

a first plurality of switches coupled to the first plurality of controlled reactance modules, each switch of the first plurality of switches responsive to a corresponding switching coefficient of the first plurality of switching coefficients to couple a control voltage to a corresponding controlled reactance module; and

a first divider coupled to the reference harmonic oscillator, the first divider adapted to provide a second reference signal at a second frequency.

26. The integrated circuit of claim 25, wherein the reference harmonic oscillator is further adapted to provide the first reference signal without locking to an external reference signal.

27. The integrated circuit of claim 25, further comprising:

a control circuit coupled to the first plurality of controlled reactance modules, the control circuit adapted to provide, in a second operating mode, a time-dependent switching of the plurality of control voltages to provide a spread-spectrum first reference signal having a plurality of different first frequencies over time.

28. The integrated circuit of claim 25, further comprising:

a second plurality of switches coupled to the first plurality of controlled reactance modules, each switch of the second plurality of switches responsive to a control signal to couple a selected controlled reactance module to a ground or power voltage.

29. The integrated circuit of claim 25, further comprising:

a second plurality of controlled reactance modules; and

a control circuit coupled to the second plurality of controlled reactance modules, the control circuit adapted to provide, in a second operating mode, a time-dependent switching of the second plurality of controlled reactance modules to the harmonic oscillator to provide a spread-spectrum first reference signal having a plurality of different first frequencies over time.

30. The integrated circuit of claim 25, wherein the divider circuit is configurable for selection of a signal type of a plurality of signal types of the second reference signal, the plurality of signal types comprising at least one of the following signal types:

differential, single-ended, full voltage rail-to-full voltage rail, or fractional voltage rail-to-fractional voltage rail.

31. The integrated circuit of claim 25, further comprising:

a plurality of locking circuits coupled to the first divider, the plurality of locking circuits adapted to lock to the second reference signal and provide a corresponding plurality of third reference signals having a plurality of corresponding third frequencies, each third frequency of the plurality of corresponding third frequencies determined from the second frequency and a divide ratio of the corresponding locking circuit of the plurality of locking circuits.

32. The integrated circuit of claim 31, further comprising:

a control circuit coupled to the plurality of locking circuits, the control circuit adapted to provide a time-dependent variance of the divide ratio of a first locking circuit of the plurality of locking circuits to provide a spread-spectrum third reference signal having a plurality of different third frequencies over time.

33. The integrated circuit of claim 31, wherein each locking circuit of the plurality of locking circuits is at least one of the following locking circuits:

a phase-locked loop, a delay-locked loop, or an injection locking circuit.

34. The integrated circuit of claim 31, wherein each locking circuit of the plurality of locking circuits is configurable for selection of the divide ratio.

35. The integrated circuit of claim 31, further comprising:

a plurality of output circuits; and

second switching circuitry coupled to the plurality of locking circuits and to the plurality of output circuits, the second switching circuitry adapted to selectively switch a selected, third reference signal of the plurality of third reference signals to a selected output circuit of the plurality of output circuits.

36. The integrated circuit of claim 35, wherein each output circuit of the plurality of output circuits is configurable for selection of a signal level of a plurality of signal levels for output of a corresponding third reference signal of the plurality of third reference signals.

37. The integrated circuit of claim 35, further comprising:

control circuitry coupled to the second switching circuitry, the control circuitry adapted to provide a control signal to the second switching circuitry to switch the selected, third reference signal to the selected output circuit.

38. The integrated circuit of claim 35, further comprising:

a second coefficient register coupled to the second switching circuitry, the second coefficient register adapted to provide a control coefficient of a second plurality of control coefficients to the second switching circuitry to switch the selected, third reference signal to the selected output circuit.

39. The integrated circuit of claim 35, wherein the second switching circuitry comprises a plurality of multiplexers and demultiplexers, or a plurality of pass-transistors, or a cross-bar switch.

40. The integrated circuit of claim 25, wherein the first plurality of controlled reactance modules further comprise:

a plurality of variable capacitors, each variable capacitor of the plurality of variable capacitors adapted to provide a corresponding capacitance in response to the control voltage.

41. The integrated circuit of claim 40, further comprising:

a second plurality of controlled reactance modules comprising a plurality of fixed capacitors, each fixed capacitor of the plurality of fixed capacitors adapted to provide a selected capacitance; and

a second plurality of switches coupled to the second plurality of controlled reactance modules, each switch of the second plurality of switches responsive to a corresponding switching coefficient of a second plurality of switching coefficients to couple a corresponding controlled reactance module of the second plurality of controlled reactance modules to the reference harmonic oscillator.

42. The integrated circuit of claim 41, wherein the second plurality of switching coefficients is determined post-fabrication by calibration to a second reference frequency signal.

43. The integrated circuit of claim 41, further comprising:

a user interface coupled to the first coefficient register, the user interface adapted to provide a coefficient of the first plurality of switching coefficients or second plurality of control coefficients to the first coefficient registers in response to user input.

44. The integrated circuit of claim 41, wherein the first frequency is mask programmable through selection of a size of the inductor, through selection of a plurality of connections of the first and second pluralities of controlled reactance modules, or through selection of a plurality of sizes of the first and second pluralities of controlled reactance modules.

45. The integrated circuit of claim 41, wherein the first frequency is configurable post-fabrication through selection of a plurality of connections of the first and second pluralities of controlled reactance modules.

46. The integrated circuit of claim 25, wherein the reference harmonic oscillator has at least one configuration of the following configurations:

a double-balanced, differential LC configuration;

a differential n-MOS cross-coupled topology;

a differential p-MOS cross-coupled topology;

a single-ended Colpitts LC configuration;

a single-ended Hartley LC configuration;

a differential, common base Colpitts LC configuration;

a differential, common collector Colpitts LC configuration;

a differential, common base Hartley LC configuration;

a differential, common collector Hartley LC configuration;

a single-ended Pierce LC oscillator, or a quadrature LC oscillator configuration.

47. The integrated circuit of claim 25, further comprising:

a variable current source adapted to provide a corresponding current in response to ambient or operating temperature.

48. The integrated circuit of claim 47, wherein the variable current source has at least one complementary to absolute temperature (CTAT) configuration, proportional to absolute temperature (PTAT) configuration, or proportional to absolute temperature squared (PTAT²) configuration.

49. A configurable integrated circuit comprising:

a reference oscillator comprising an inductor, a capacitor, and an amplifier, the reference oscillator adapted to provide a first reference signal having a first frequency without locking to an external reference signal;

a voltage controller adapted to provide a control voltage;

a first plurality of controlled reactance modules coupled to the reference oscillator and to the voltage controller, each reactance module of the plurality of reactance modules adapted to provide a selected reactance in response to the control voltage to maintain the first frequency substantially constant in a first operating mode;

a first divider coupled to the reference oscillator, the first divider adapted to provide a second reference signal at a second frequency; and

a locking circuit coupled to the first divider, the locking circuit adapted to lock to the second reference signal and provide a third reference signal having a third frequency determined from the second frequency and a divide ratio of the locking circuit.

50. The configurable integrated circuit of claim 49, further comprising:

a control circuit coupled to the locking circuit, the control circuit adapted to provide a time-dependent configuration of the divide ratio of the locking circuit to provide a spread-spectrum third reference signal having a plurality of different third frequencies over time.

51. The integrated circuit of claim 49, further comprising:

a second plurality of controlled reactance modules;

a coefficient register coupled to the second plurality of controlled reactance modules, the coefficient register adapted to store a plurality of coefficients and to provide a corresponding coefficient to control switching of a corresponding controlled reactance module of the second plurality of controlled reactance modules to the reference oscillator.

52. The configurable integrated circuit of claim 49, further comprising:

a control circuit coupled to the coefficient register, the control circuit adapted to provide, in a second operating mode, a time-dependent switching of the second plurality of controlled reactance modules to the reference oscillator to provide a spread-spectrum first reference signal having a plurality of different first frequencies over time.

53. The configurable integrated circuit of claim 49, wherein the oscillator has at least one configuration of the following configurations:

a double-balanced, differential LC configuration;

a differential n-MOS cross-coupled topology;

a differential p-MOS cross-coupled topology;

a single-ended Colpitts LC configuration;

a single-ended Hartley LC configuration;

a differential, common base Colpitts LC configuration;

a differential, common collector Colpitts LC configuration;

a differential, common base Hartley LC configuration;

a differential, common collector Hartley LC configuration;

a single-ended Pierce LC oscillator, or a quadrature LC oscillator configuration.