Device and method for monitoring operation of a flash memory

• US 7,657,699 B2
• Filed: 04/07/2006
• Issued: 02/02/2010
• Est. Priority Date: 11/09/2005
• Status: Active Grant

• Current Assignee: Western Digital Israel Limited (Western Digital Corporation)
• Original Assignee: SanDisk IL Ltd. (Western Digital Corporation)
• Inventors: Shlick, Mark, Murin, Mark
• Primary Examiner(s): Bragdon; Reginald G
• Assistant Examiner(s): Mackall; Larry T
• Application Number:
  US11/399,343
• Publication Number:
  US 20070106834A1
• Time in Patent Office: 1,397 Days
• Field of Search: None
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

A flash memory device includes an array of memory cells for storing data pages, at least one buffer (e.g. a memory buffer and a cache buffer) for transferring the data pages to and from the array of memory cells and a host, and an output pin. A logic mechanism is operative to select, from among a plurality of conditions related to an operation on the array of memory cells, a condition that drives a signal being output on the output pin. A data page transfer by the host is contingent on the signal being output on the output pin.

Claims

1. A flash memory device comprising:

(a) an array of memory cells for storing data pages;

(b) at least one buffer for transferring said data pages between said array of memory cells and a host;

(c) an output pin dedicated only to having driven thereon a signal reflective of a condition from among a plurality of conditions of the flash memory device that are related to operation of said array of memory cells; and

(d) a logic mechanism that is operative to select, in response to at least one command from a host of the flash memory device, a first condition from among said plurality of conditions, said first condition for driving said signal, said signal has a value that changes in response to changes in said first condition.

2. The flash memory device of claim 1, wherein said selected condition is that said array of memory cells is busy.

3. The flash memory device of claim 1, wherein said selected condition is that one buffer of said at least one buffer is busy.

4. The flash memory device of claim 1, wherein said selected condition is a compound condition that one or both of said array of memory cells and said buffer is busy.

5. The flash memory device of claim 1, wherein said selected condition is a failure of an operation.

6. The flash memory device of claim 1, wherein said selected condition is a logical operational state selected from the group consisting of:

a page program failure and a block erase failure.

7. The flash memory device of claim 1, wherein said at least one command operates said logic mechanism to toggle said condition each time said at least one command is received.

8. The flash memory device of claim 1, wherein said logic mechanism maintains said selection until an event selected from the group consisting of:

a reset command and a powering up is encountered.

9. The flash memory device of claim 1, wherein said logic mechanism maintains said selection during an activation of only a single command.

10. The flash memory device of claim 1, wherein each of said at least one command corresponds to a different respective condition.

11. A method for monitoring operation of a flash memory device, the flash device having an output pin, the method comprising the steps of:

(a) sending a command to the flash memory device instructing the flash memory device to select a condition, from among a plurality of conditions, under which a state of an output pin changes in response to a ready/busy condition of said memory device, wherein said state of said output pin represents a single bit that is fully indicative of said selected condition until a different said single condition is selected in response to a sending of a subsequent command to the flash memory device; and

(c) interrogating said selected condition by sensing a change in the state of said output pin that occurs in response to said ready/busy condition.

12. The method of claim 11, wherein said selected condition is a compound condition of whether one or both of a memory array of said memory device and a buffer of said memory device is busy.

13. The method of claim 11, wherein, once said single condition has been selected and until another condition of the plurality is selected, said signal indicates only said selected single condition.

14. A flash memory device comprising:

a memory array of memory cells for storing data;

a buffer for transferring said data between said memory array and a host that is external to said memory device;

an output pin, a value on the output pin indicates a ready/busy condition of the memory device, the ready busy condition is one of a plurality of ready/busy conditions of the memory device involving the memory array and the buffer; and

a logic mechanism that is operative to receive a command from the host, the command identifies a first ready/busy condition of the plurality of ready/busy conditions, the logic mechanism causes the output pin to output a first value that specifies the first ready/busy condition, the first value on the output pin changes in response to the first ready/busy condition.

15. The flash memory device of claim 14 wherein the plurality of ready/busy conditions include whether the memory array is busy and whether the buffer is busy.

16. The flash memory device of claim 14 wherein the plurality of ready/busy conditions include a ready/busy condition of the memory array, a ready/busy condition of the buffer, and a ready/busy condition that involves both the memory array and the buffer.

17. The flash memory device of claim 14, wherein the plurality of ready/busy conditions include a failure of an operation involving the memory array.

18. The flash memory device of claim 14 wherein the first signal represents a single bit that is fully indicative of the first ready/busy condition until a different single condition is selected in response to a subsequent command from the host.

19. A method of operating a flash memory device, the method comprising:

outputting a first hardware signal on a pin of the flash memory device, the first hardware signal has a value that specifies a first ready/busy condition out of a plurality of ready/busy conditions of the memory device;

receiving a command from a host of the flash memory device while the first hardware signal is being output, the command identifies a second ready/busy condition of the memory device out of the plurality of ready/busy conditions;

outputting a second hardware signal on the pin of the flash memory device in response to receiving the command, the second hardware signal has a value that specifies the second ready/busy condition;

detecting a change in the second ready/busy condition of the memory device while outputting the second hardware signal; and

changing the value of the second hardware signal on the pin to reflect the change in the second ready/busy condition.

20. The method of claim 19 wherein the plurality of ready/busy conditions include a ready/busy condition of a memory array of the memory device, a ready/busy condition of a buffer that is coupled to the memory array, and a ready/busy condition that involves both the memory array and the buffer.

21. The method of claim 20 further comprising:

receiving a unit of data from the host to be stored in the memory array;

storing the unit of data in the buffer;

transferring the unit of data from the buffer to the memory array, the first ready/busy condition is whether the buffer is busy, the second busy/ready condition is whether the memory array is busy.

22. The method of claim 20 wherein the command includes a parameter that specifies the second ready/busy condition.

23. A flash memory device comprising:

a memory array of memory cells for storing data;

a buffer for transferring said data between said memory array and a host that is external to said memory device;

a selector circuit that inputs a first hardware signal that specifies whether the memory array is busy or ready and a second hardware signal that specifies whether the buffer is busy or ready, the selector circuit is operative to form a third hardware signal that is a logical combination of whether the memory array is busy and whether the buffer is busy;

an output pin coupled to the selector circuit, the output pin is dedicated to providing a single bit value that is one of the first hardware signal, the second hardware signal, and the third hardware signal, and

a logic mechanism that is operative to receive a command from the host, the command identifies either a ready/busy condition of the memory array, a ready/busy condition of the buffer, or a logical combination of a ready/busy condition of the memory array and a ready/busy condition of the buffer, the logic mechanism controls the selector circuit to cause the output pin to output one of the first hardware signal, the second hardware signal, or the third hardware signal depending on what the command identifies.