High speed memory and input/output processor subsystem for efficiently allocating and using high-speed memory and slower-speed memory

• US 7,657,706 B2
• Filed: 12/17/2004
• Issued: 02/02/2010
• Est. Priority Date: 12/18/2003
• Status: Expired

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: McKeown, Nick, Iyer, Sundar
• Primary Examiner(s): KIM, HONG CHONG
• Application Number:
  US11/016,572
• Publication Number:
  US 20050240745A1
• Time in Patent Office: 1,873 Days
• Field of Search: 709/250, 710/15, 710/36, 711/117, 711/118, 711/170, 711/202, 711/109, 711/221, 712/34, 712/36, 718/102
• US Class Current: 711/117
• CPC Class Codes: G06F 12/0223 User address space allocation, e.g. contiguous or non contiguous base addressing
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G06F 2212/205 Hybrid memory, e.g. using both volatile and non-volatile memory

Abstract

An input/output processor for speeding the input/output and memory access operations for a processor is presented. The key idea of an input/output processor is to functionally divide input/output and memory access operations tasks into a compute intensive part that is handled by the processor and an I/O or memory intensive part that is then handled by the input/output processor. An input/output processor is designed by analyzing common input/output and memory access patterns and implementing methods tailored to efficiently handle those commonly occurring patterns. One technique that an input/output processor may use is to divide memory tasks into high frequency or high-availability components and low frequency or low-availability components. After dividing a memory task in such a manner, the input/output processor then uses high-speed memory (such as SRAM) to store the high frequency and high-availability components and a slower-speed memory (such as commodity DRAM) to store the low frequency and low-availability components. Another technique used by the input/output processor is to allocate memory in such a manner that all memory bank conflicts are eliminated. By eliminating any possible memory bank conflicts, the maximum random access performance of DRAM memory technology can be achieved.

Claims

1. A method of improving performance for a computer processor, said method comprising:

receiving in an input/output processor data and a memory access instruction from said computer processor, said memory access instruction identifying a type of memory storage task from a group of more than one different memory storage task;

analyzing said memory access instruction in said input/output processor to identify said type of memory storage task;

if said type of memory storage task comprises a counter adjustment then

updating a value containing recent adjustments to said counter in a higher-speed memory, and

updating a full version of said counter in a slower-speed memory if an overflow of said value containing recent adjustments to said counter occurs; and

if said type of memory storage task comprises a write to a FIFO queue then

storing said data in a queue tail of said FIFO queue in said higher-speed memory, and

moving data from said queue tail to a queue body of said FIFO queue in said slower-speed memory if said queue tail is filled.

2. The method as claimed in claim 1 wherein said higher-speed memory comprises static random access memory (SRAM).

3. The method as claimed in claim 1 wherein said slower-speed memory comprises dynamic random access memory (DRAM).

4. The method as claimed in claim 1 wherein said a FIFO queue further comprises a tail of said FIFO queue in said higher-speed memory.

5. The method as claimed in claim 1, said method further comprising:

if said type of memory storage task comprises a counter read then

generating a sum by adding said value containing recent adjustments to said counter to said full version of said counter in said slower speed memory, and returning said sum.

6. The method as claimed in claim 1, said method further comprising:

if said type of memory storage task comprises a read from said FIFO queue then

responding with data from in a queue head of said FIFO queue in said higher-speed memory, and

moving data from said queue body of said FIFO queue in said slower-speed memory to said queue head in said higher-speed memory.