Integrated circuit with embedded test functionality

• US 7,657,807 B1
• Filed: 06/27/2005
• Issued: 02/02/2010
• Est. Priority Date: 06/27/2005
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Watkins, Daniel R., Donahue, Hunter S., Ziaja, Thomas Alan
• Primary Examiner(s): Ellis; Kevin L
• Assistant Examiner(s): Merant; Guerrier
• Application Number:
  US11/167,248
• Time in Patent Office: 1,681 Days
• Field of Search: None
• US Class Current: 714/727
• CPC Class Codes: G01R 31/318594 Timing aspects clock circuits G01R31/318552

Abstract

An integrated circuit including embedded test functionality. An integrated circuit may include a plurality of processor cores each configured to execute instructions, and a test access port configured to interface circuits included within the integrated circuit with a test environment external to the integrated circuit for testing of the circuits. The test access port may include virtualization logic configured to allow a first set of instructions executing on the given processor core to control activity of the test access port for testing of the circuits. In one embodiment, the circuits may be accessible for testing via a plurality of scan chains, wherein the scan chains and the test access port are compliant with a version of Joint Test Access Group (JTAG) standard IEEE 1149, and wherein the test access port includes a Test Data In (TDI) pin, a Test Data Out (TDO) pin, and a Test Clock (TCK) pin.

Claims

1. An integrated circuit, comprising:

a plurality of processor cores each configured to execute instructions; and

a test access port configured to interface circuits included within the integrated circuit with a test environment external to the integrated circuit for testing of said circuits;

wherein said test access port includes virtualization logic configured to allow a first set of instructions executing on a given one of said plurality of processor cores to control activity of said test access port for testing of said circuits.

2. The integrated circuit as recited in claim 1, wherein said circuits are accessible for testing via a plurality of scan chains, wherein said scan chains and said test access port are compliant with the Joint Test Access Group (JTAG) standard IEEE 1149.1-1990, and wherein said test access port includes a Test Data In (TDI) pin, a Test Data Out (TDO) pin, and a Test Clock (TCK) pin.

3. The integrated circuit as recited in claim 2, wherein said virtualization logic includes one or more control registers configured to control said TDI, TDO and TCK pins of said test access port in response to being programmed by instructions executing on said given processor core.

4. The integrated circuit as recited in claim 1, wherein said first set of instructions executing on said given processor core is configurable to perform functional testing via said test access port of any circuit included within said integrated circuit that is accessible via said test access port.

5. The integrated circuit as recited in claim 1, wherein said first set of instructions executing on said given processor core is configurable to perform transition testing via said test access port of any circuit included within said integrated circuit that is accessible via at least one scan chain.

6. The integrated circuit as recited in claim 1, further comprising a serializer/deserializer (serdes) circuit configured to directly or indirectly interface one or more of said processor cores with peripheral logic included within said integrated circuit, wherein said first set of instructions executing on said given processor core is configurable to monitor operating behavior of said serdes circuit and to adjust operating parameters of said serdes circuit in response to said monitoring.

7. The integrated circuit as recited in claim 1, further comprising a serializer/deserializer (serdes) circuit configured to directly or indirectly interface one or more of said processor cores with peripheral logic included within said integrated circuit, wherein said serdes circuit is accessible for testing via said test access port, and wherein said first set of instructions executing on said given processor core is configurable to perform functional testing of said serdes circuit via said test access port.

8. The integrated circuit as recited in claim 1, wherein instructions executed by each of said processor cores are user-programmable and wherein the instructions executed by said processor cores are dynamically configurable during operation of said processor cores.

9. The integrated circuit as recited in claim 1, wherein each of said processor cores is associated with a respective plurality of threads, and wherein each of said processor cores is configured to issue a first instruction from one of said respective plurality of threads during one execution cycle and to issue a second instruction from another one of said respective plurality of threads during a successive execution cycle.

10. The integrated circuit as recited in claim 9, wherein said first set of instructions is associated with a first one of said respective plurality of threads associated with a first one of said processor cores, wherein said first thread is configured to execute concurrently with other threads executing on said processor cores.

11. The integrated circuit as recited in claim 10, wherein one of said other threads includes instructions configured to implement one or more of an operating system or an application program.

12. The integrated circuit as recited in claim 10, wherein said first set of instructions associated with said first thread is configured to monitor operation of one or more of said circuits included within said integrated circuit while one or more of said other threads concurrently executes.

13. The integrated circuit as recited in claim 12, wherein in response to detecting an error condition associated with a monitored one of said circuits, said first set of instructions is configured to capture current state information associated with said monitored circuit for analysis.

14. The integrated circuit as recited in claim 12, wherein in response to detecting an error condition associated with a monitored one of said circuits, said first set of instructions is configured to capture historical state information associated with previous activity of said monitored circuit for analysis.

15. A method of testing an integrated circuit including a test access port configured to interface circuits included within the integrated circuit with a test environment external to the integrated circuit for testing of said circuits and a plurality of processor cores each independently programmable to execute instructions, the method comprising:

testing said integrated circuit via said test environment external to said integrated circuit to determine whether said integrated circuit includes sufficient functional resources to execute specific embedded testing instructions;

in response to determining that said integrated circuit includes sufficient functional resources to execute said specific embedded testing instructions, loading said specific embedded testing instructions into said integrated circuit from said external test environment via said test access port for execution by a given one of said processor cores; and

said given processor core executing said specific embedded testing instructions independently of said external test environment;

wherein said test access port includes virtualization logic configured to allow said embedded testing instructions executing on said given processor core to control activity of said test access port for testing of said circuits.

16. The method as recited in claim 15, wherein said circuits are accessible for testing via a plurality of scan chains, wherein said scan chains and said test access port are compliant with the Joint Test Access Group (JTAG) standard IEEE 1149.1-1990, and wherein said test access port includes a Test Data In (TDI) pin, a Test Data Out (TDO) pin, and a Test Clock (TCK) pin.

17. The method as recited in claim 16, wherein said virtualization logic includes one or more control registers configured to control said TDI, TDO and TCK pins of said test access port in response to being programmed by said embedded testing instructions executing on said given processor core.

18. The method as recited in claim 15, wherein said embedded testing instructions executing on said given processor core are configurable to perform functional testing via said test access port of any circuit included within said integrated circuit that is accessible via said test access port.

19. The method as recited in claim 15, wherein said embedded testing instructions executing on said given processor core is configurable to perform transition testing via said test access port of any circuit included within said integrated circuit that is accessible via at least one scan chain.

20. A system, comprising:

a system memory; and

a processor coupled to said system memory, wherein said processor includes;

a plurality of processor cores each configured to execute instructions; and

a test access port configured to interface circuits included within the integrated circuit with a test environment external to the integrated circuit for testing of said circuits;

wherein said test access port includes virtualization logic configured to allow a first set of instructions executing on a given one of said plurality of processor cores to control activity of said test access port for testing of said circuits.

21. An integrated circuit, comprising:

a processor core configured to execute instructions;

peripheral logic coupled to said processor core; and

a test access port configured to interface circuits included within the integrated circuit with a test environment external to the integrated circuit for testing of said circuits;

wherein said test access port includes virtualization logic configured to allow a first set of instructions executing on said processor core to control activity of said test access port for testing of said peripheral logic.

22. The integrated circuit as recited in claim 21, wherein said peripheral logic includes a serializer/deserializer (serdes) circuit configured to directly or indirectly interface said processor core with other logic included within said integrated circuit, wherein said serdes circuit is accessible for testing via said test access port, and wherein said first set of instructions is configurable to test said serdes circuit via said test access port.