Method for processing data

• US 7,657,877 B2
• Filed: 06/20/2002
• Issued: 02/02/2010
• Est. Priority Date: 06/20/2001
• Status: Active Grant

• Current Assignee: Scientia Sol Mentis AG (PACT XPP Schweiz AG)
• Original Assignee: Pact XPP Technologies, AG
• Inventors: Vorbach, Martin, May, Frank, Weinhardt, Markus, Nuckel, Armin, Cardoso, Joao Manuel Paiva
• Primary Examiner(s): Zhen; Wei Y
• Assistant Examiner(s): Brophy; Matthew J
• Application Number:
  US10/480,003
• Publication Number:
  US 20040243984A1
• Time in Patent Office: 2,784 Days
• Field of Search: 717136-161
• US Class Current: 717/141
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 8/45 Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions

Abstract

A method and device for translating a program to a system including at least one first processor and a reconfigurable unit. Code portions of the program which are suitable for the reconfigurable unit are determined. The remaining code of the program is extracted and/or separated for processing by the first processor.

Claims

1. A method for translating a data processing program for a system including at least one first processor and a reconfigurable unit, the method comprising:

determining from the program, code portions of the program suitable for the reconfigurable unit;

extracting the determined code portions for processing by the reconfigurable unit;

extracting remaining code portions of the program for processing by the first processor; and

appending interface code to at least one of (a) the code portions extracted for the reconfigurable unit and (b) the code portions extracted for the first processor, the appended interface code controlling communication of data to be processed between the first processor and the reconfigurable unit and enabling communication between the reconfigurable unit and the first processor by one of (a) transferring the data to be processed via dedicated memory areas and (b) transferring base addresses of memory locations in which the data to be processed is located;

wherein;

the data to be processed is processed by the reconfigurable unit via execution of the determined code portions; and

the suitability determination includes consideration of a plurality of factors, the plurality of factors including a data type of the data to be processed and a size of the data to be processed.

2. The method as recited in claim 1, wherein the determining step includes determining the code portions based on automated analyses.

3. The method as recited in claim 1, wherein the program includes instructions defining the code portions to be extracted, and wherein the method further comprises automatically analyzing the instructions.

4. The method as recited in claim 1, wherein the code portions to be extracted are determined based on calls of subprograms.

5. The method as recited in claim 1, wherein the interface code provides at least one of memory linkage, register linkage, and linkage via a network.

6. The method as recited in claim 1, further comprising:

analyzing at least one of the extracted code portions and results achievable with a given extraction; and

restarting an extraction with new improved parameters based on the analysis.

7. The method as recited in claim 1, further comprising:

appending control code to the extracted code for at least one of management, control, and communication of the development system.

8. The method as recited in claim 1, wherein the first processor includes at least one of a von-Neumann architecture, Harvard architecture, controller, CISC processor, RISC processor, VLIW processor, and DSP processor.

9. The method as recited in claim 1, wherein the remaining code is extracted so that it is translatable via any ordinary unmodified compiler that is suitable for the first processor.

10. The method as recited in claim 1, wherein the appended interface code is system specific so that it enables the communication according to the system.

11. The method as recited in claim 1, wherein the code portions are executable by both the first processor and the reconfigurable unit.

12. The method as recited in claim 1, further comprising:

in accordance with reconfiguration data, reconfiguring the reconfigurable unit for execution of the determined code portions to process the data to be processed.

13. The method as recited in claim 1, wherein:

the reconfigurable unit includes a plurality of configurable elements;

in accordance with reconfiguration data, a reconfiguration unit configures the plurality of configurable elements for processing the data to be processed, the data to be processed being communicated between the first processor and one or more of the plurality of configurable elements in a communication that bypasses the reconfiguration unit.

14. The method as recited in claim 13, wherein the reconfigurable unit includes the reconfiguration unit.

15. A method for translating a data processing program for a system including at least one first processor and a reconfigurable unit, the method comprising:

determining from the program, code portions of the program suitable for the reconfigurable unit;

extracting the determined code portions for processing by the reconfigurable unit;

extracting remaining code portions of the program for processing by the first processor;

modifying at least one of (a) the code portions extracted for the reconfigurable unit and (b) the code portions extracted for the first processor to include interface code that controls communication of data to be processed between the first processor and the reconfigurable unit, and that enables communication between the reconfigurable unit and the first processor by one of (a) transferring the data to be processed via dedicated memory areas and (b) transferring base addresses of memory locations in which the data to be processed is located; and

compiling the modified code by at least one compiler;

wherein;

the data to be processed is processed by the reconfigurable unit via execution of the determined code portions; and

the suitability determination includes consideration of a plurality of factors, the plurality of factors including a data type of the data to be processed and a size of the data to be processed.

16. A device for data processing, comprising:

a first processor;

a reconfigurable unit; and

an arrangement configured to perform a method to translate a data processing program, the method including;

determining from the program, code portions of the program suitable for the reconfigurable unit;

extracting the determined code portions for processing by the reconfigurable unit;

extracting remaining code portions of the program for processing by the first processor; and

modifying at least one of (a) the code portions extracted for the reconfigurable unit and (b) the code portions extracted for the first processor to include interface code that controls communication of data to be processed between the first processor and the reconfigurable unit, and that enables communication between the reconfigurable unit and the first processor by one of (a) transferring the data to be processed via dedicated memory areas and (b) transferring base addresses of memory locations in which the data to be processed is located;

wherein;

the data to be processed is processed by the reconfigurable unit via execution of the determined code portions; and

the suitability determination includes consideration of a plurality of factors, the plurality of factors including a data type of the data to be processed and a size of the data to be processed.

17. The device as recited in claim 16, wherein:

the device is configured to exchange the data to be processed and status information between the first processor and the reconfigurable unit, wherein the exchange is at least one of;

i) during processing of one or more programs, ii) without having to interrupt data processing on the reconfigurable processor, and iii) without having to interrupt data processing on the first processor; and

,

the status information indicates a status of operations including at least one of zero, carry, overflow, equal, ready, not-ready, and error.

18. The device as recited in claim 16, wherein the determination is based on calls of subprograms.

19. The device as recited in claim 16, wherein the method further comprises:

analyzing at least one of the extracted code portions and results achievable with a given extraction; and

restarting an extraction with new improved parameters based on the analysis.

20. The device as recited in claim 16, wherein the determination includes determining the code portions based on automated analyses.