Semiconductor device and method of manufacturing the same, circuit board, and electronic instrument

• US 7,659,142 B2
• Filed: 07/29/2008
• Issued: 02/09/2010
• Est. Priority Date: 03/23/1998
• Status: Expired due to Fees

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Hashimoto, Nobuaki
• Primary Examiner(s): Thai; Luan C
• Application Number:
  US12/219,833
• Publication Number:
  US 20080305587A1
• Time in Patent Office: 560 Days
• Field of Search: 438/106, 438/614, 438/612, 438/613, 257/E23.021, 257/E23.023
• US Class Current: 438/106
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/02125 Reinforcing structures
• CPC Class Codes: H01L 2224/0236 Shape of the insulating layers therebetween
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/051 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/05111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05171 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05551 comprising apertures or cavities
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05671 Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/06131 being uniform, i.e. having a uniform pitch across the array
• CPC Class Codes: H01L 2224/13 : of an individual bump connector
• CPC Class Codes: H01L 2224/13024 : the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/10 : Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01021 : Scandium [Sc]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A semiconductor device comprising: a semiconductor element having a plurality of electrodes; a passivation film formed on the semiconductor element in a region avoiding at least a part of each of the electrodes; a conductive foil provided at a given spacing from the surface on which the passivation film is formed; an external electrodes formed on the conductive foil; intermediate layer formed between the passivation film and the conductive foil to support the conductive foil; and wires electrically connecting the electrodes to the conductive foil; wherein a depression tapered in a direction from the conductive foil to the passivation film if formed under a part of the conductive foil that includes the connection with the external electrodes.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

providing a semiconductor chip on which an electrode and a passivation film is formed;

forming a metal film on the passivation film;

forming a resin layer such that the resin layer has a first portion, a second portion and a first hole, the first portion being formed on the passivation film, the second portion being formed on a first part of the metal film, the first hole being disposed on a second part of the metal film;

forming a conductive foil electrically connected to the electrode above the first hole such that the first hole being interposed between the second part of the metal film and the conductive foil and a first part of the conductive foil being disposed above the second part of the metal film; and

forming an external electrode on the first part of the conductive foil such that the external electrode is positioned above the first hole.

2. The method of manufacturing a semiconductor device according to claim 1, the forming of the resin layer including:

forming the resin layer on the semiconductor chip such that a part of the resin layer is formed on the metal film; and

etching the part of the resin layer formed on the metal film such that the first hole is formed on the second part of the metal film.

3. The method of manufacturing a semiconductor device according to claim 2, a material of the resin layer not being etched under the etching conditions of the resin layer.

4. The method of manufacturing a semiconductor device according to claim 3, the passivation film being formed of a material which is etched under the etching condition of the resin layer.

9. The method of manufacturing a semiconductor device according to claim 1, further comprising:

forming a wire electrically insulated with the metal film such that the wire has a first part and a second part, the first part of the wire being formed on the electrode, the second part of the wire being formed on the resin layer; and

forming the conductive foil electrically connected to the electrode through the wire.

11. The method of manufacturing a semiconductor device according to claim 1, further comprising:

forming a solder resist layer such that the solder resist layer has a second hole, the second hole being disposed on the first part of the conductive foil; and

forming the external electrode on the first part of the conductive foil within the second hole.

5. A method of manufacturing an electronic component, the method comprising:

providing a base substrate on which an electrode and a passivation film is formed;

forming a metal film on the passivation film;

forming a resin layer such that the resin layer has a first portion, a second portion and a first hole, the first portion being formed on the passivation film, the second portion being formed on a first part of the metal film, the first hole being disposed on a second part of the metal film;

forming a conductive foil electrically connected to the electrode above the first hole such that the first hole being interposed between the second part of the metal film and the conductive foil and a first part of the conductive foil being disposed above the second part of the metal film; and

forming an external electrode on the first part of the conductive foil such that the external electrode is positioned above the first hole.

6. The method of manufacturing an electronic component according to claim 5, the forming of the resin layer including:

forming the resin layer on the semiconductor chip such that a part of the resin layer is formed on the metal film; and

etching the part of the resin layer formed on the metal film such that the first hole is formed on the second part of the metal film.

7. The method of manufacturing an electronic component according to claim 6, a material of the resin layer not being etched under the etching conditions of the resin layer.

8. The method of manufacturing a semiconductor device according to claim 7, the passivation film is being formed of a material which is etched under the etching condition of the resin layer.

10. The method of manufacturing an electronic component according to claim 5, further comprising:

forming a wire electrically insulated with the metal film such that the wire has a first part and a second part, the first part of the wire being formed on the electrode, the second part of the wire being formed on the resin layer; and

forming the conductive foil electrically connected to the electrode through the wire.

12. The method of manufacturing an electronic component according to claim 5, further comprising:

forming a solder resist layer such that the solder resist layer has a second hole, the second hole being disposed on the first part of the conductive foil; and

forming the external electrode on the first part of the conductive foil within the second hole.