Semiconductor device and method of forming stepped-down RDL and recessed THV in peripheral region of the device

• US 7,659,145 B2
• Filed: 07/14/2008
• Issued: 02/09/2010
• Est. Priority Date: 07/14/2008
• Status: Active Grant

• Current Assignee: JCET Semiconductor (Shaoxing) Co., Ltd.
• Original Assignee: Stats Chippac Limited
• Inventors: Chua, Linda Pei Ee, Do, Byung Tai, Kuan, Heap Hoe, Pagaila, Reza A.
• Primary Examiner(s): POTTER, ROY KARL
• Application Number:
  US12/172,817
• Publication Number:
  US 20100007029A1
• Time in Patent Office: 575 Days
• Field of Search: 257/774, 438/109, 438/667
• US Class Current: 438/109
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05611 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/82001 involving a temporary auxiliary member not forming part of the bonding apparatus
• CPC Class Codes: H01L 2224/82039 using a laser
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/0103 : Zinc [Zn]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

A semiconductor die has a peripheral region around the die. An insulating layer is formed over the semiconductor die. A portion of the insulating layer and peripheral is removed to form a recess around the semiconductor die. A conductive layer is deposited over the insulating layer and recess. The conductive layer is electrically connected to contact pads on the semiconductor die and conforms to a step into the recess. A gap is created through the conductive layer and peripheral region around the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a through hole via (THV). A conductive material is deposited in the THV to form a conductive THV. The conductive THV is recessed with respect to a surface of the semiconductor die. The conductive THV is electrically connected to the conductive layer.

Claims

1. A method of making a semiconductor device, comprising:

providing a semiconductor wafer having a plurality of semiconductor die each with a peripheral region around the semiconductor die;

forming an insulating layer over the semiconductor wafer;

removing a portion of the insulating layer and peripheral region to form a recess around the semiconductor die;

depositing a first conductive layer over the insulating layer and recess, the first conductive layer being electrically connected to contact pads on the semiconductor die and conforming to a step into the recess;

creating a gap through the first conductive layer and peripheral region around the semiconductor die;

depositing an insulating material in the gap;

removing a portion of the insulating material to form a through hole via (THV);

depositing a conductive material in the THV to form a conductive THV, the conductive THV being recessed with respect to a surface of the semiconductor die, the conductive THV being electrically connected to the first conductive layer; and

singulating the semiconductor wafer through the gap to separate the semiconductor die.

2. The method of claim 1, wherein singulating the semiconductor wafer occurs through the conductive THV in the gap to form a conductive half-via.

3. The method of claim 1, wherein singulating the semiconductor wafer occurs through the insulating material in the gap to form a conductive full-via.

4. The method of claim 1, further including forming a masking layer over the insulating material prior to depositing the conductive material.

5. The method of claim 1, further including removing a portion of the insulating layer to expose the contact pads.

6. The method of claim 1, wherein creating the gap includes:

cutting through the semiconductor wafer less than a width of the peripheral region around the semiconductor die; and

moving the semiconductor die apart to expand the gap.

7. The method of claim 1, further including forming a second conductive layer over the insulating material and conductive material to electrically connect the conductive material to the first conductive layer.

8. A method of making a semiconductor device, comprising:

providing a semiconductor wafer having a plurality of semiconductor die each with a peripheral region around the semiconductor die;

forming an insulating layer over the semiconductor wafer;

removing a portion of the insulating layer and peripheral region to form a recess around the semiconductor die;

creating a gap through the peripheral region around the semiconductor die;

depositing an insulating material in the gap;

depositing a conductive layer over the insulating layer and insulating material, the conductive layer being electrically connected to contact pads on the semiconductor die;

removing a portion of the insulating material to form a through hole via (THV);

depositing a conductive material in the THV to form a conductive THV, the conductive THV being electrically connected to the conductive layer; and

singulating the semiconductor wafer through the gap to separate the semiconductor die.

9. The method of claim 8, wherein singulating the semiconductor wafer occurs through the conductive THV in the gap to form a conductive half-via.

10. The method of claim 8, wherein singulating the semiconductor wafer occurs through the insulating material in the gap to form a conductive full-via.

11. The method of claim 8, further including forming a masking layer over the insulating material prior to depositing the conductive material.

12. The method of claim 8, further including removing a portion of the insulating layer to expose the contact pads.

13. The method of claim 8, wherein creating the gap includes:

cutting through the semiconductor wafer less than a width of the peripheral region around the semiconductor die; and

moving the semiconductor die apart to expand the gap.

14. A method of making a semiconductor device, comprising:

providing a semiconductor die having a peripheral region around the semiconductor die;

forming an insulating layer over the semiconductor die;

removing a portion of the insulating layer and peripheral region to form a recess around the semiconductor die;

depositing a first conductive layer over the insulating layer and recess, the first conductive layer being electrically connected to contact pads on the semiconductor die and conforming to a step into the recess;

creating a gap through the first conductive layer and peripheral region around the semiconductor die;

depositing an insulating material in the gap;

removing a portion of the insulating material to form a through hole via (THV); and

depositing a conductive material in the THV to form a conductive THV, the conductive THV being recessed with respect to a surface of the semiconductor die, the conductive THV being electrically connected to the first conductive layer.

15. The method of claim 14, wherein singulating the semiconductor wafer occurs through the conductive THV to form a conductive half-via.

16. The method of claim 14, wherein singulating the semiconductor wafer occurs through the insulating material in the gap to form a conductive full-via.

17. The method of claim 14, further including forming a masking layer over the insulating material prior to depositing the conductive material.

18. The method of claim 14, further including removing a portion of the insulating layer to expose the contact pads.

19. The method of claim 14, wherein creating the gap includes:

cutting through the semiconductor wafer less than a width of the peripheral region around the semiconductor die; and

moving the semiconductor die apart to expand the gap.

20. The method of claim 14, further including forming a second conductive layer over the insulating material and conductive material to electrically connect the conductive material to the first conductive layer.