Dual metal gate finFETs with single or dual high-K gate dielectric

• US 7,659,157 B2
• Filed: 09/25/2007
• Issued: 02/09/2010
• Est. Priority Date: 09/25/2007
• Status: Active Grant

• Current Assignee: Auriga Innovations, Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: Greene, Brian J., Kumar, Mahender
• Primary Examiner(s): Tran; Long K
• Application Number:
  US11/860,840
• Publication Number:
  US 20090078997A1
• Time in Patent Office: 868 Days
• Field of Search: 438/199, 438/157, 438/313, 438/322, 438/213, 438/592, 257/283, 257/E21.242, 257/E21.703, 257/E21.63, 257/E21.631, 257/E21.632
• US Class Current: 438/199
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A first high-k gate dielectric layer and a first metal gate layer are formed on first and second semiconductor fins. A first metal gate ring is formed on the first semiconductor fin. In one embodiment, the first high-k gate dielectric layer remains on the second semiconductor fin. A second metal gate layer and a silicon containing layer are deposited and patterned to form gate electrodes. In another embodiment, a second high-k dielectric layer replaces the first high-k dielectric layer over the second semiconductor fin, followed by formation of a second metal gate layer. A first electrode comprising a first gate dielectric and a first metal gate is formed on the first semiconductor fin, while a second electrode comprising a second gate dielectric and a second metal gate is formed on the second semiconductor fin. Absence of high-k gate dielectric materials on a gate wiring prevents increase in parasitic resistance.

Claims

1. A method of forming a semiconductor structure comprising:

providing a first semiconductor fin and a second semiconductor fin on a substrate;

forming a first high-k gate dielectric layer surrounding and laterally abutting said first semiconductor fin;

forming a first high-k gate dielectric ring surrounding and laterally abutting said first semiconductor fin and another first high-k gate dielectric ring surrounding and laterally abutting said second semiconductor fin;

forming a first metal gate ring surrounding and laterally abutting said first high-k gate dielectric layer and forming another first metal gate ring surrounding and laterally abutting said another first high-k gate dielectric ring;

removing said another first high-k gate ring and said another first metal gate ring, while protecting said first high-k gate dielectric ring and said first metal gate ring with a block mask;

forming a second metal gate layer on said first semiconductor fin and said second semiconductor fin; and

forming a silicon containing layer directly on a portion of said second metal gate layer.

2. The method of claim 1, further comprising:

patterning said silicon containing layer so that a remaining portion of said silicon containing layer intersects said first and second semiconductor fins in a top-down view; and

removing exposed portions of said second metal gate layer, said first high-k gate dielectric layer, and said first metal gate ring from outside the area covered by said remaining portion of said silicon containing layer.

3. The method of claim 2, further comprising forming a first metal gate comprising two remaining disjoined portions of said first metal gate ring underneath said remaining portion of said silicon containing layer, wherein a portion of said patterned silicon containing layer, a portion of said second metal gate layer, and said first metal gate collectively constitute a first gate electrode controlling a current flow in said first semiconductor fin, and wherein another portion of said patterned silicon containing layer and another portion of said second metal gate layer collectively constitute a second gate electrode controlling a current flow in said second semiconductor fin.

4. The method of claim 2, further comprising:

forming a first metal gate comprising two remaining disjoined portions of said first metal gate ring underneath said remaining portion of said silicon containing layer, wherein a portion of said patterned silicon containing layer and said first metal gate collectively constitute a first gate electrode controlling a current flow in said first semiconductor fin; and

forming a second metal gate comprising two remaining disjoined portions of said second metal gate layer underneath said remaining portion of said silicon containing layer, wherein another portion of said patterned silicon containing layer and said second metal gate collectively constitute a second gate electrode controlling a current flow in said second semiconductor fin.

8. The method of claim 1, further comprising:

forming a first metal gate layer directly on said first high-k gate dielectric layer; and

etching said first high-k gate dielectric layer and forming a first high-k gate dielectric ring.

9. The method of claim 8, further comprising:

forming a first fin spacer surrounding and laterally abutting a portion of said first metal gate layer on said first semiconductor fin and another first fin spacer surrounding and laterally abutting another portion of said first metal gate layer on said second semiconductor fin prior to said forming a first metal gate ring; and

removing said another fin spacer prior to said forming of said second metal gate layer.

10. The method of claim 8, further comprising:

forming a first fin spacer surrounding and laterally abutting a portion of said first metal gate layer on said first semiconductor fin and another first fin spacer surrounding and laterally abutting another portion of said first metal gate layer on said second semiconductor fin prior to said forming a first metal gate ring;

forming a second fin spacer surrounding and laterally abutting a portion of said second metal gate layer on said second semiconductor fin and another second fin spacer surrounding and laterally abutting another portion of said second metal gate layer on said first semiconductor fin after said forming of said second metal gate layer; and

removing said another second fin spacer, while protecting said second fin spacer with a block mask.

11. The method of claim 8, wherein said first high-k gate dielectric ring has an L-shaped vertical cross-sectional area and has a shape that is topologically homeomorphic to a torus.

12. The method of claim 8, wherein said substrate comprises an insulator layer vertically abutting said first semiconductor fin and said second semiconductor fin, and wherein said first metal gate ring laterally abuts outer sidewalls of said first high-k gate dielectric ring, vertically abuts a top surface of a laterally protruding bottom portion of said first high-k gate dielectric ring, and has a shape that is topologically homeomorphic to a torus.

5. A method of forming a semiconductor structure comprising:

providing a first semiconductor fin and a second semiconductor fin on a substrate;

forming a first high-k gate dielectric layer surrounding and laterally abutting said first semiconductor fin;

forming a first metal gate ring surrounding and laterally abutting said first high-k gate dielectric layer;

forming a second metal gate layer on said first semiconductor fin and said second semiconductor fin;

forming a silicon containing layer directly on a portion of said second metal gate layer; and

forming a second high-k gate dielectric layer directly on said second semiconductor fin and directly on said first metal gate prior to said forming of said second metal gate layer, wherein said second metal gate layer is formed directly on said second high-k gate dielectric layer.

6. The method of claim 5, further comprising:

forming a second high-k gate dielectric ring surrounding and laterally abutting said second semiconductor fin; and

forming a second metal gate ring surrounding and laterally abutting said second high-k gate dielectric ring.

7. The method of claim 6, further comprising:

forming another second high-k gate dielectric ring surrounding and laterally abutting said first metal gate ring; and

forming another second metal gate ring surrounding and laterally abutting said another second high-k gate dielectric ring;

removing said another second high-k gate ring and said another second metal gate ring, while protecting said second high-k gate dielectric ring and said second metal gate ring with a block mask.