Method of forming transistor using step STI profile in memory device

• US 7,659,179 B2
• Filed: 12/29/2005
• Issued: 02/09/2010
• Est. Priority Date: 03/31/2005
• Status: Expired due to Fees

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Hu, Hyun
• Primary Examiner(s): Toledo; Fernando L
• Assistant Examiner(s): Singal; Ankush K
• Application Number:
  US11/322,843
• Publication Number:
  US 20060223263A1
• Time in Patent Office: 1,503 Days
• Field of Search: 438/221, 438/297, 438/424, 438/435
• US Class Current: 438/418
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND

Abstract

A method of forming a memory device includes forming first and second isolation structures on a semiconductor substrate, the first and second isolation structures defining an active region therebetween; and etching a portion of the semiconductor substrate provided within the active region to define a step profile, so that the active region includes a first vertical portion and an upper primary surface, the first vertical portion extending above the upper primary surface.

Claims

1. A method of forming a memory device, comprising:

forming first and second isolation structures on a semiconductor substrate, the first and second isolation structures defining an active region therebetween;

forming STI spacers on sidewalls of the first and the second isolation structures;

forming a trench having a width narrower than a distance between the first isolation structure and the second isolation structure to form a step profile in the active region by etching the semiconductor substrate using the STI spacers as an etching mask; and

forming a doped region to be used as a source region or a drain region in a bottom side of the trench and in a sidewall of the trench by performing an ion implantation process,

wherein the doped region is formed after forming the first and second isolation structures.

2. The method of claim 1, wherein the STI spacers are formed to a thickness of 100 Å

to 1000 Å

.

3. The method of claim 1, wherein the slanted implantation method involves implanting the dopants into the active region using an implantation angle of 4-15 degrees.

4. The method of claim 1, wherein the vertical implantation method involves implanting the dopants into the active region using an implantation angle of substantially 0 degree.

5. The method of claim 1, wherein the STI spacers are formed using one of an oxide film or a nitride film.

6. The method of claim 1, the method further comprising:

performing an annealing process to form an oxide film;

removing the oxide film, using a wet etching process, leaving corners of the STI profiles rounded; and

forming a tunnel oxide film over the semiconductor substrate within the active region using a radical oxidization process.

7. The method of claim 2, wherein the STI spacers are formed using LP-TEOS, HTO, or MTO.

8. The method of claim 6, wherein the oxide film is formed at a temperature between 800°

C. and 1100<

C. and a thickness of 10 Å

to 30 Å

.

10. The method of claim 1, wherein the ion implantation process includes a vertical implantation and a slanted implantation methods.

9. A method of forming a memory device, comprising:

forming first and second isolation structures on a semiconductor substrate, the first and second isolation structures defining an active region therebetween;

forming first and second spacers provided adjacent to the first and second isolation structures, respectively, the first and second spacers exposing a portion of the substrate;

etching the exposed portion of the substrate to define a step profile, so that the active region includes first and second vertical portions and an upper primary surface, the first and second vertical portions extending above the upper primary surface, the first vertical portion being provided directly below the first spacer, the second vertical portion being provided directly below the second spacer;

forming a doped region to be used as a source region or a drain region in a bottom side of the step profile and in a sidewall of the step profile by performing an ion implantation process, wherein the doped region is formed after forming the first and second isolation structures;

annealing the semiconductor substrate after the etching step to round a corner defined by the step profile;

removing an oxide film formed over the substrate as a result of the annealing; and

thereafter, forming a tunnel oxide over the semiconductor substrate within the active region, wherein the tunnel oxide is formed using a radical oxidization process.

11. The method of claim 9, wherein the ion implantation process includes a vertical implantation and a slanted implantation methods.