Semiconductor device including a floating gate memory cell with a superlattice channel

• US 7,659,539 B2
• Filed: 05/05/2006
• Issued: 02/09/2010
• Est. Priority Date: 06/26/2003
• Status: Active Grant

• Current Assignee: Atomera Incorporated
• Original Assignee: Mears Technologies Incorporated
• Inventors: Kreps, Scott A., Rao, Kalipatnam Vivek
• Primary Examiner(s): Pham; Long
• Application Number:
  US11/381,787
• Publication Number:
  US 20060243963A1
• Time in Patent Office: 1,376 Days
• Field of Search: 257/20, 257/28, 257/288, 257/314
• US Class Current: 257/28
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence

Abstract

A semiconductor device may include a semiconductor substrate and at least one non-volatile memory cell. The at least one memory cell may include spaced apart source and drain regions, and a superlattice channel including a plurality of stacked groups of layers on the semiconductor substrate between the source and drain regions. Each group of layers of the superlattice channel may include a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon, which may include at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A floating gate may be adjacent the superlattice channel, and a control gate may be adjacent the second gate insulating layer.

Claims

1. A semiconductor device comprising:

a semiconductor substrate; and

at least one nonvolatile memory cell comprising a superlattice channel comprising a plurality of stacked groups of layers on said semiconductor substrate, spaced apart source and drain regions for causing transport of charge carriers through said superlattice channel in a parallel direction relative to the stacked groups of layers,

each group of layers of said superlattice channel comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and an energy band-modifying layer thereon,

said energy band-modifying layer comprising at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions, and at least some semiconductor atoms from opposing base semiconductor portions being chemically bound together with the chemical bonds traversing the at least one non-semiconductor monolayer therebetween,

a floating gate adjacent said superlattice channel, and

a control gate adjacent said floating gate.

2. The semiconductor device of claim 1 wherein said nonvolatile memory cell further comprises a first insulating layer between said floating gate and said control gate.

3. The semiconductor device of claim 2 wherein said at least one nonvolatile memory cell further comprises a second insulating layer between said superlattice channel and said floating gate.

4. The semiconductor device of claim 1 wherein said at least one nonvolatile memory cell further comprises a superlattice insulating layer between said floating gate and said control gate.

5. The semiconductor device of claim 1 further comprising a contact layer on at least one of said source and drain regions.

6. The semiconductor device of claim 1 wherein said superlattice channel has a common energy band structure therein.

7. The semiconductor device of claim 1 wherein said superlattice channel has a higher charge carrier mobility than would otherwise be present without said energy band-modifying layer.

8. The semiconductor device of claim 1 wherein each base semiconductor portion comprises silicon.

9. The semiconductor device of claim 1 wherein each base semiconductor portion comprises germanium.

10. The semiconductor device of claim 1 wherein each energy band-modifying layer comprises oxygen.

11. The semiconductor device of claim 1 wherein each energy band-modifying layer is a single monolayer thick.

12. The semiconductor device of claim 1 wherein each base semiconductor portion is less than eight monolayers thick.

13. The semiconductor device of claim 1 wherein said superlattice channel further has a substantially direct energy bandgap.

14. The semiconductor device of claim 1 wherein said superlattice channel further comprises a base semiconductor cap layer on an uppermost group of layers.

15. The semiconductor device of claim 1 wherein all of said base semiconductor portions are a same number of monolayers thick.

16. The semiconductor device of claim 1 wherein at least some of said base semiconductor portions are a different number of monolayers thick.

17. The semiconductor device of claim 1 wherein each energy band-modifying layer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.