Manufacturing method of semiconductor device

• US 7,659,574 B2
• Filed: 08/31/2007
• Issued: 02/09/2010
• Est. Priority Date: 06/25/2004
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Kubo, Sakae, Nakazawa, Yoshito
• Primary Examiner(s): Mandala; Victor A
• Assistant Examiner(s): STOWE, SCOTT C
• Application Number:
  US11/849,015
• Publication Number:
  US 20080173938A1
• Time in Patent Office: 893 Days
• Field of Search: 257/328, 257/330, 257/335, 257/341, 257/342, 257/E27.055, 257/E27.074, 257/E29.024, 257/E29.025, 257/E29.026, 257/E29.027, 257/E29.028
• US Class Current: 257/330
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A power MISFET, which has a desired gate breakdown voltage, can be manufactured will controlling an increase in parasitic capacitance. After depositing a polycrystalline silicon film on a substrate and embedding groove portions in the polycrystalline silicon film by patterning the polycrystalline silicon film in an active cell area, a gate electrode is formed within the groove portion, and the inside of the groove portion is embedded in a gate wiring area. Extending to the outside of the groove portion continuously out of the groove portion, there is a gate drawing electrode electrically connected to the gate electrode. Slits extending from the end portion of the gate drawing electrode are formed in the gate drawing electrode outside of the groove portion. Then, a silicon oxide film and a BPSG film are deposited on the substrate.

Claims

1. A semiconductor device having a MOSFET, comprising:

a semiconductor substrate having a main surface and a back surface opposite to the main surface, said semiconductor substrate including an active cell area and a gate wiring area, and said semiconductor substrate having a first conductivity type;

a well region in the main surface in the active cell area, said well region having a second conductivity type opposite to the first conductivity type;

a first groove portion in the main surface in the active cell area, said first groove portion penetrating the well region;

a gate oxide film of the MOSFET on an inner surface of the first groove portion;

a gate electrode of the MOSFET over the gate oxide film, said gate electrode being in the first groove portion;

a source region of the MOSFET in the well region in the active cell area, said source region contacting the first groove portion, and said source region having the first conductivity type;

a gate drawing electrode over the main surface in said gate wiring area such that an upper surface of the gate drawing electrode is higher than an upper surface of the gate electrode, said gate drawing electrode being integrally formed with the gate electrode;

an insulating film over the gate electrode and gate drawing electrode, the insulating film having an opening therein in the gate wiring area, said opening extending through the insulating film to the gate drawing electrode;

a gate wiring over the insulating film and electrically connected with the gate drawing electrode through the opening;

a source electrode over the insulating film and electrically connected with the source region in the active cell area;

and a drain electrode over the back surface and electrically connected with the semiconductor substrate having the first conductivity type, wherein an upper surface of the gate electrode is lower than the main surface of the semiconductor substrate so as to form a second groove portion in the active cell area, and wherein the insulating film is disposed inside the second groove portion, wherein the gate drawing electrode has a first part and a second part adjoining to the first part, the first part of the gate drawing electrode has a plurality of slits in a plan view, the insulating film is disposed inside the plurality of slits, and the opening extends to the first part of the gate drawing electrode.

2. A semiconductor device according to claim 1, wherein the first part of the gate drawing electrode is divided by the plurality of slits.

3. A semiconductor device according to claim 1, wherein the insulating film is comprised of a Boro-Phospho Silicate Glass film.

4. A semiconductor device according to claim 1, wherein the gate wiring and source electrode are comprised of a same conductive layer.

5. A semiconductor device according to claim 1, wherein the gate wiring and source electrode are comprised of an aluminum layer.

6. A semiconductor device according to claim 1, wherein the plurality of slits do not extend to an end of the gate drawing electrode.

7. A semiconductor device according to claim 1, wherein the plurality of slits extend to an end of the gate drawing electrode.

17. A semiconductor device according to claim 1, wherein the insulating film is disposed inside the second groove portion such that the insulating film exposes the source region where the source electrode is electrically connected to the source region.

22. A semiconductor device according to claim 1, wherein the insulating film is disposed inside the plurality of slits such that the insulating film exposes the plurality of slits where the gate wiring is electrically connected to the plurality of slits.

8. A semiconductor device having a MOSFET, comprising:

a semiconductor substrate having a main surface and a back surface opposite to the main surface, said semiconductor substrate including an active cell area and a gate wiring area, and said semiconductor substrate having a first conductivity type;

a well region in the main surface in the active cell area, said well region having a second conductivity type opposite to the first conductivity type;

a first groove portion in the main surface in the active cell area, said first groove portion penetrating the well region;

a gate oxide film of the MOSFET on an inner surface of the first groove portion;

a gate electrode of the MOSFET over the gate oxide film, said gate electrode being in the first groove portion;

a source region of the MOSFET in the well region in the active cell area, said source region contacting the first groove portion, and said source region having the first conductivity type;

a gate drawing electrode over the main surface in said gate wiring area such that an upper surface of the gate drawing electrode is higher than an upper surface of the gate electrode, said gate drawing electrode being integrally formed with the gate electrode;

an insulating film over the gate electrode and gate drawing electrode, the insulating film having an opening therein in the gate wiring area, said opening extending though the insulating film to the gate drawing electrode;

a gate wiring over the insulating film and electrically connected with the gate drawing electrode though the opening;

a source electrode over the insulating film and electrically connected with the source region in the active cell area; and

a drain electrode over the back surface and electrically connected with the semiconductor substrate having the first conductivity type, wherein the gate drawing electrode has a first part and a second part adjoining to the first part, the first part of the gate drawing electrode has a second groove portion in a plan view, the insulating film is disposed inside the second groove portion, and the opening extends to the first part of the gate drawing electrode, wherein an upper surface of the gate electrode is lower than the main surface of the semiconductor substrate so as to form a third groove portion in the active cell area, and wherein the insulating film is disposed inside the third groove portion.

9. A semiconductor device according to claim 8, wherein the first part of the gate drawing electrode is divided by the second groove portion.

10. A semiconductor device according to claim 8, wherein the insulating film is comprised of a Boro-Phospho Silicate Glass film.

11. A semiconductor device according to claim 8, wherein the gate wiring and source electrode are comprised of a same conductive layer.

12. A semiconductor device according to claim 8, wherein the gate wiring and source electrode are comprised of an aluminum layer.

13. A semiconductor device according to claim 8, wherein the second groove portion is a plurality of openings in the first part of the gate drawing electrode.

14. A semiconductor device according to claim 8, wherein the second groove portion is a plurality of slits in the first part of the gate drawing electrode, and wherein the plurality of slits do not extend to an end of the gate drawing electrode.

15. A semiconductor device according to claim 8, wherein the second groove portion is a plurality of slits in the first part of the gate drawing electrode, and wherein the plurality of slits extend to an end of the gate drawing electrode.

16. A semiconductor device according to claim 8, wherein the second groove portion is a plurality of recesses in the first part of the gate drawing electrode.

18. A semiconductor device according to claim 8, wherein the insulating film is disposed inside the third groove portion such that the insulating film exposes the source region where the source electrode is electrically connected to the source region.

23. A semiconductor device according to claim 8, wherein the insulating film is disposed inside the second groove portion such that the insulating film exposes the first part of the gate drawing electrode where the gate wiring is electrically connected to the first part of the gate drawing electrode.

19. A semiconductor device having a MOSFET, comprising:

a semiconductor substrate having a main surface and a back surface opposite to the main surface, the semiconductor substrate including an active cell area and a gate wiring area, and the semiconductor substrate having a first conductivity type;

a well region in the main surface in the active cell area, the well region having a second conductivity type opposite to the first conductivity type;

a first groove portion in the main surface in the active cell area, the first groove portion penetrating the well region;

a gate oxide film of the MOSFET on an inner surface of the first groove portion;

a gate electrode of the MOSFET over the gate oxide film, the gate electrode being in the first groove portion such that a upper surface of the gate electrode is lower than the main surface of the semiconductor substrate so as to form a second groove;

a source region of the MOSFET in the well region in the active cell area, the source region contacting the groove portion, and the source region having the first conductivity type;

a gate drawing electrode over the main surface in the gate wiring area, the gate drawing electrode being integrally formed with the gate electrode;

an insulating film over the gate drawing electrode and inside the second groove such that the insulating film exposes the source region, the insulating film having an opening in the gate wiring area;

a gate wiring over the insulating film and electrically connected with the gate drawing electrode through the opening;

a source electrode over the insulating film and electrically connected with the source region in the active cell area; and

a drain electrode over the back surface and electrically connected with the semiconductor substrate having the first conductivity type,

wherein the gate drawing electrode has a first part and a second part adjoining to the first part,

the first part of the gate drawing electrode has a plurality of slits in a plan view,

the insulating film is disposed inside the plurality of slits, and

the opening extends to the first part of the gate drawing electrode.

20. A semiconductor device according to claim 19, wherein the first part of the gate drawing electrode is divided by the plurality of slits.

21. A semiconductor device according to claim 19, wherein the insulating film is disposed inside the plurality of slits such that the insulating film exposes the plurality of slits where the gate wiring is electrically connected to the plurality of slits.