Semiconductor device having variable thickness insulating film and method of manufacturing same

• US 7,659,578 B2
• Filed: 10/11/2005
• Issued: 02/09/2010
• Est. Priority Date: 10/12/2004
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Mobile Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Kang, Tae-Wook
• Primary Examiner(s): Luu; Chuong A.
• Application Number:
  US11/247,470
• Publication Number:
  US 20060076618A1
• Time in Patent Office: 1,582 Days
• Field of Search: 257/336, 257/347, 257/72, 257/40, 257/59, 257/149, 257/151, 257/89, 257/296, 257/298, 257/300, 257/303, 257/306, 257/308
• US Class Current: 257/336
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile

Abstract

Embodiments of a semiconductor device capable of increasing an aperture ratio of an organic electroluminescence display device by decreasing the surface area of a capacitor in the organic electroluminescence display device and a method of manufacturing the semiconductor device are disclosed. By forming a gate insulating film of a gate electrode with a thickness different from that of a dielectric film of a capacitor, the surface area of the capacitor can be decreased without variation in capacitance, thereby increasing the aperture ratio of an organic electroluminescence display device.

Claims

1. A semiconductor device comprising:

first and second semiconductor-layer patterns formed on a substrate, wherein the second semiconductor-layer pattern forms a capacitor;

an insulating film formed substantially on the entire surface of the substrate including the first and second semiconductor-layer patterns, wherein the insulating film has a first thickness on a part of the first semiconductor-layer pattern and on the second semiconductor-layer pattern, and a second thickness on a central portion of the first semiconductor-layer pattern, wherein the first thickness is less than the second thickness; and

a plurality of conductive-layer patterns formed on the insulating film so as to cover the central portion of the first semiconductor-layer pattern and so as to cover the second semiconductor-layer pattern.

2. The semiconductor device according to claim 1, wherein the first semiconductor-layer pattern forms an NMOS thin film transistor.

3. The semiconductor device according to claim 1, wherein the first semiconductor-layer pattern comprises a channel region, source and drain regions, and a Lightly Doped Drain (LDD) area, and the second semiconductor-layer pattern forms a lower electrode of the capacitor.

4. The semiconductor device according to claim 1, wherein the first conductive-layer pattern forms a gate electrode and the second conductive-layer pattern forms an upper electrode of the capacitor.

5. The semiconductor device according to claim 1, wherein the insulating film is a gate insulating film.

6. The semiconductor device according to claim 1, wherein the insulating film comprises one of silicon oxide and silicon nitride.

7. The semiconductor device according to claim 1, wherein the surface area A′

of a capacitor comprising the semiconductor-layer pattern, the insulating film, and the conductive-layer pattern in the second area satisfies the following equation;

16. The semiconductor device according to claim 1, wherein the capacitor comprises a polysilicon layer.

18. The semiconductor device according to claim 1, wherein the insulating film forms a dielectric of a capacitor in the second semiconductor-layer pattern and a gate insulation layer of a thin film transistor in the first semiconductor-layer pattern.

8. A semiconductor device comprising:

first, second, and third semiconductor-layer patterns formed on a substrate, wherein the third semiconductor-layer pattern forms at least a portion of a capacitor;

an insulating film formed substantially on the entire surface of the substrate including the first, second and third semiconductor-layer patterns, wherein the insulating film has a first thickness on a part of the second semiconductor-layer pattern and on the third semiconductor-layer pattern, and a second thickness on the first semiconductor-layer pattern and on a central portion of the second semiconductor-layer pattern, wherein the first thickness is less than the second thickness; and

a plurality of conductive-layer patterns formed on the insulating film to cover the central portion of the first and second semiconductor-layer patterns and to cover the third semiconductor-layer pattern.

9. The semiconductor device according to claim 8, wherein the first semiconductor-layer pattern forms at least a portion of a PMOS thin film transistor, and the second semiconductor-layer pattern forms at least a portion of an NMOS thin film transistor.

10. The semiconductor device according to claim 8, wherein the first and second conductive-layer patterns comprise gate electrodes, and the third conductive-layer pattern comprises an upper electrode of the capacitor.

11. The semiconductor device according to claim 8, wherein the first and second semiconductor-layer patterns each comprise a channel region and source and drain regions, and the third semiconductor-layer pattern forms a lower electrode of the capacitor.

12. The semiconductor device according to claim 11, wherein the second semiconductor-layer pattern further includes a Lightly Doped Drain (LDD) region.

13. The semiconductor device according to claim 8, wherein the insulating film is a gate insulating film.

14. The semiconductor device according to claim 8, wherein the insulating film comprises at least one of silicon oxide and silicon nitride.

15. The semiconductor device according to claim 8, wherein the surface area A′

of the capacitor, comprising a portion of the third semiconductor-layer pattern, a portion of the insulating film, and a portion of a conductive-layer pattern in the third area satisfies the following equation;

17. The semiconductor device according to claim 8, wherein the capacitor comprises a polysilicon layer.

19. The semiconductor device according to claim 8, wherein the insulating film forms a dielectric of a capacitor in the third semiconductor-layer pattern and a gate insulation layer of a thin film transistor in the second semiconductor-layer pattern.