Resistor circuit

• US 7,659,765 B2
• Filed: 05/25/2006
• Issued: 02/09/2010
• Est. Priority Date: 06/07/2005
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Ito, Koichi
• Primary Examiner(s): Wells; Kenneth B.
• Application Number:
  US11/911,637
• Publication Number:
  US 20090284311A1
• Time in Patent Office: 1,356 Days
• Field of Search: 327/308
• US Class Current: 327/308
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2203/45638 the LC comprising one or more coils
• CPC Class Codes: H03F 2203/45641 the LC being controlled, e.g. by a signal derived from a non specified place in the dif amp circuit
• CPC Class Codes: H03F 2203/45686 the LC comprising one or more potentiometers, which are not shunting potentiometers
• CPC Class Codes: H03F 2203/45691 the LC comprising one or more transistors as active loading resistors
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03H 11/245 using field-effect transistor

Abstract

Operations as a variable resistor are favorably realized even when a drain-source voltage of a variable MOS resistor and that of a reference MOS resistor are not the same. A gate voltage of the variable MOS resistor is controlled with reference to a gate voltage which is controlled such that a voltage generated in the reference MOS resistor is controlled to be the same as a reference voltage. A resistor is connected in parallel with the reference MOS resistor between the drain and source thereof, the resistor including a pair of resistors having the same resistance connected in series. Half of a drain-source voltage of the reference MOS resistor is detected at an intermediate point of the pair of resistors. The gate voltage of the variable resistor is obtained by subtracting one-half of the drain-source voltage from the gate voltage of the reference MOS resistor.

Claims

1. A resistor circuit comprising:

a reference MOS resistor;

a variable MOS resistor;

first control means for controlling a gate voltage of the reference MOS resistor such that a resistance of the reference MOS resistor is controlled to be constant;

voltage detection means for detecting half of a drain-source voltage of the reference MOS resistor; and

second control means for controlling the variable resistor by supplying a gate voltage of the variable MOS resistor on the basis of the gate voltage of the reference MOS resistor controlled by the first control means and half the drain-source voltage of the reference MOS resistor detected by the voltage detection means.

2. The resistor circuit according to claim 1, wherein the first control means includes means for detecting a voltage generated in the reference MOS resistor and means for controlling the voltage generated in the reference MOS resistor to be the same as a predetermined reference voltage.

3. The resistor circuit according to claim 1, wherein the voltage detection means includes a resistor unit connected in parallel with the reference MOS resistor between a drain and source thereof, the resistor unit including two resistors having the same resistance connected in series, and wherein half the drain-source voltage of the reference MOS resistor is detected at an intermediate point of the resistor unit having the resistors connected in series.

4. The resistor circuit according to claim 1, wherein the reference MOS resistor and the variable MOS resistor are of a PMOS type or an nMOS type.

5. The resistor circuit according to claim 1 further comprising second voltage detection means for detecting half of a drain-source voltage of the variable MOS resistor,

wherein the second control means controls the variable resistor by supplying a voltage as the gate voltage of the variable MOS resistor, the voltage being obtained by subtracting half the drain-source voltage of the reference MOS resistor detected by the voltage detection means from, and adding half the drain-source voltage of the variable MOS resistor detected by the second voltage detection means to, the gate voltage of the reference MOS resistor controlled by the first control means.

6. The resistor circuit according to claim 5, wherein the second voltage detection means includes a resistor unit connected in parallel with the variable MOS resistor between a drain and source thereof, the resistor unit including two resistors having the same resistance connected in series, and wherein half the drain-source voltage of the variable MOS resistor is detected at an intermediate point of the resistor unit having the resistors connected in series.

7. A load circuit comprising the variable MOS resistor according to claim 1.

8. A differential amplifier circuit, wherein the variable MOS resistor according to claim 1 is inserted as an output load between output terminals of the differential amplifier circuit.

9. A communication apparatus, wherein the variable MOS resistor according to claim 1 is implemented as a load resistor within at least one of a transmission amplifier and a reception amplifier.