High frequency switching circuit
First Claim
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1. A high frequency switching circuit comprising:
- first and second high frequency signal terminals;
a first control terminal;
a power supply terminal;
a first field-effect transistor having a drain, a source, a gate, and a back gate, the first field-effect transistor being connected between the first and the second high frequency signal terminals to switch higher frequency signals;
a first variable resistance circuit connected between the gate of the first field-effect transistor and the first control terminal; and
a second variable resistance circuit connected between the back gate and the power supply,wherein each of the resistance values of the first and the second variable resistance circuits is lower in an OFF state of the first field-effect transistor than in an ON state of the first field-effect transistor.
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Abstract
A high frequency switching circuit is disclosed. The high frequency switching circuit is provided with first and second high frequency signal terminals, a control terminal, a field-effect transistor having a drain, a source and a gate. The field-effect transistor is connected between the first and the second high frequency signal terminals so as to switch a high frequency signal. The high frequency switching circuit is further provided with a variable resistance circuit which is connected between the gate of the field-effect transistor and the control terminal.
49 Citations
20 Claims
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1. A high frequency switching circuit comprising:
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first and second high frequency signal terminals; a first control terminal; a power supply terminal; a first field-effect transistor having a drain, a source, a gate, and a back gate, the first field-effect transistor being connected between the first and the second high frequency signal terminals to switch higher frequency signals; a first variable resistance circuit connected between the gate of the first field-effect transistor and the first control terminal; and a second variable resistance circuit connected between the back gate and the power supply, wherein each of the resistance values of the first and the second variable resistance circuits is lower in an OFF state of the first field-effect transistor than in an ON state of the first field-effect transistor. - View Dependent Claims (2, 3, 4, 5, 6, 18)
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7. A high frequency switching circuit comprising:
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first and second high frequency signal terminals; a power supply terminal; a first control terminal; a first field-effect transistor having a drain, a source and a gate, the first field-effect transistor being connected between the first and the second high frequency signal terminals to switch a higher frequency signal; a second field-effect transistor having a drain, a source, a gate and a back gate, the second field-effect transistor being connected between the first high frequency signal terminal and the power supply terminal; a third variable resistance circuit connected between the gate of the second field-effect transistor and the second control terminal; and a fourth variable resistance circuit connected between the back gate of the second field-effect transistor and the power supply terminal, wherein each of the resistance values of the third and the fourth variable resistance circuits is lower in an OFF state of the second field-effect transistor than in an ON state of the second field-effect transistor. - View Dependent Claims (8, 9, 10, 19)
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11. A high frequency switching circuit comprising:
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a pair of first high frequency signal terminals; a second high frequency signal terminal serving as a common high frequency signal terminal; first and second control terminals; a power supply terminal; a pair of first field-effect transistors respectively having a drain, a source a gate and a back gate, the first field-effect transistors being respectively connected between the first high frequency signal terminals and the second high frequency signal terminal a pair of first variable resistance circuits connected between the gates of the first field-effect transistors and the first and second control terminals respectively; and a pair of second variable resistance circuits connected between the back gate of the first field-effect transistors and the power supply terminal, wherein each of the resistance values of the first and the second variable resistance circuits is lower in an OFF state of the first field-effect transistors than in an ON state of the first field-effect transistors. - View Dependent Claims (12, 13, 14, 15, 16, 17, 20)
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Specification