Video and graphics system with parallel processing of graphics windows

• US 7,659,900 B2
• Filed: 07/12/2006
• Issued: 02/09/2010
• Est. Priority Date: 11/09/1998
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: MacInnis, Alexander G., Tang, Chengfuh Jeffrey, Kranawetter, Greg A.
• Primary Examiner(s): Brier; Jeffery A
• Application Number:
  US11/485,582
• Publication Number:
  US 20070030276A1
• Time in Patent Office: 1,308 Days
• Field of Search: 345501-506, 345/558, 345/619, 345/629, 345563-569, 348563-570
• US Class Current: 345/505
• CPC Class Codes: G06T 9/007 Transform coding, e.g. discrete cosine transform
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2310/0224 Details of interlacing
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2340/0428 Gradation resolution change
• CPC Class Codes: G09G 2340/06 Colour space transformation
• CPC Class Codes: G09G 2340/10 Mixing of images, i.e. displayed pixel being the result of an operation, e.g. adding, on the corresponding input pixels
• CPC Class Codes: G09G 2340/12 Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 2360/128 Frame memory using a Synchronous Dynamic RAM [SDRAM]
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/02 characterised by the way in which colour is displayed details of colour display specific for CRTs G09G1/28; specific for flat matrix panels other than liquid crystal displays G09G3/2003; specific for liquid crystal displays G09G3/3607
• CPC Class Codes: G09G 5/024 using colour registers, e.g. to control background, foreground, surface filling G09G5/06 takes precedence
• CPC Class Codes: G09G 5/026 Control of mixing and/or overlay of colours in general G09G5/022 and G09G5/024 take precedence
• CPC Class Codes: G09G 5/06 : using colour palettes, e.g. look-up tables
• CPC Class Codes: G09G 5/12 : Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: G09G 5/14 : Display of multiple viewports
• CPC Class Codes: G09G 5/28 : for enhancement of character form, e.g. smoothing
• CPC Class Codes: G09G 5/346 : for systems having a bit-mapped display memory
• CPC Class Codes: G09G 5/36 : characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
• CPC Class Codes: G09G 5/363 : Graphics controllers
• CPC Class Codes: H04N 11/143 : Encoding means therefor H04N11/16 takes precedence
• CPC Class Codes: H04N 11/20 : Conversion of the manner in which the individual colour picture signal components are combined, e.g. conversion of colour television standards
• CPC Class Codes: H04N 19/112 : according to a given display mode, e.g. for interlaced or progressive display mode
• CPC Class Codes: H04N 19/16 : for a given display mode, e.g. for interlaced or progressive display mode
• CPC Class Codes: H04N 19/186 : the unit being a colour or a chrominance component
• CPC Class Codes: H04N 19/20 : using video object coding
• CPC Class Codes: H04N 19/27 : involving both synthetic and natural picture components, e.g. synthetic natural hybrid coding [SNHC]
• CPC Class Codes: H04N 19/42 : characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 : characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/436 : using parallelised computational arrangements
• CPC Class Codes: H04N 19/44 : Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/59 : involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution
• CPC Class Codes: H04N 19/61 : in combination with predictive coding
• CPC Class Codes: H04N 19/80 : Details of filtering operations specially adapted for video compression, e.g. for pixel interpolation H04N19/635, H04N19/86 take precedence
• CPC Class Codes: H04N 21/42204 : User interfaces specially adapted for controlling a client device through a remote control device; Remote control devices therefor constructive details of casings for the remote control device H01H9/0235; user interfaces for controlling a tuning device of a television receiver through a remote control H03J9/00; remote control of peripheral devices connected to a television receiver through the remote control device of the television receiver H04B1/205
• CPC Class Codes: H04N 21/426 : Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/42653 : for processing graphics
• CPC Class Codes: H04N 21/4305 : Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/4316 : for displaying supplemental content in a region of the screen, e.g. an advertisement in a separate window
• CPC Class Codes: H04N 21/434 : Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/4438 : Window management, e.g. event handling following interaction with the user interface
• CPC Class Codes: H04N 21/47 : End-user applications
• CPC Class Codes: H04N 5/126 : whereby the synchronisation signal indirectly commands a frequency generator
• CPC Class Codes: H04N 5/14 : Picture signal circuitry for video frequency region cameras or camera modules comprising electronic image sensors, or control thereof H04N23/00
• CPC Class Codes: H04N 5/44504 : Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
• CPC Class Codes: H04N 5/45 : Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 5/46 : for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 9/45 : Generation or recovery of colour sub-carriers
• CPC Class Codes: H04N 9/641 : Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence
• CPC Class Codes: H04N 9/642 : Multi-standard receivers
• CPC Class Codes: H04N 9/75 : Chroma key
• CPC Class Codes: H04N 9/78 : for separating the brightness signal or the chrominance signal from the colour television signal, e.g. using comb filter

Abstract

A display engine of a video and graphics system includes one or more processing elements and receives graphics from a memory. The graphics data define multiple graphics layers, and the processing elements process two or more graphics layers in parallel to generate blended graphics. Alpha values may be used while blending graphics. The processing elements may be integrated on an integrated circuit chip with an input for receiving the graphics data and other video and graphics components. The display engine may also include a graphics controller for receiving two or more graphics layers in parallel, for arranging the graphics layers in an order suitable for parallel processing, and for providing the arranged graphics layers to the processing elements. The blended graphics may be blended with HDTV video or SDTV video, which may be extracted from compressed data streams such as an MPEG Transport stream.

Claims

1. A video and graphics system comprising:

a plurality of graphics converters for receiving a plurality of graphics data portions, and for converting the graphics data portions to generate converted graphics data portions;

a graphics controller for receiving the converted graphics data portions and for ordering the converted graphics data portions into an order suitable for blending; and

a plurality of graphics blenders for blending the converted graphics data portions concurrently to generate a blended graphics image.

2. The video and graphics system of claim 1, wherein the plurality of graphics data portions comprise a plurality of graphics windows.

3. The video and graphics system of claim 1, wherein the graphics blenders comprise at least two first level graphics blenders and at least one second level graphics blender, and wherein each of the first level graphics blenders blend at least two of the converted graphics data portions to generate one of intermediate graphics images, and the at least one second level graphics blender blends the intermediate graphics images to generate the blended graphics image.

4. The video and graphics system of claim 3, wherein the converted graphics data portions comprise at least two upper layer data portions and at least two lower layer data portions, wherein the at least two upper layer data portions are blended by a first one of the first level graphics blenders, and the at least two lower layer data portions are blended by a second one of the first level graphics blenders, wherein the at least two upper layer data portions are blended concurrently with the blending of the at least two lower layer data portions.

5. The video and graphics system of claim 1, wherein the graphics converters generate the converted graphics data portions having a common format.

6. The video and graphics system of claim 1, further comprising a plurality of CLUTs, each CLUT being coupled to a corresponding one of the graphics converters and being used for conversion of the graphics data portions having a CLUT data format.

7. The video and graphics system of claim 1, wherein the graphics converters, the graphics controller, and the graphics blenders are implemented on a single integrated circuit chip.

8. The video and graphics system of claim 1, wherein each of the converted graphics data portions represents a plurality of pixels and at least one blending factor, wherein the graphics blenders blend the converted graphics data portions using the at least one blending factor.

9. The video and graphics system of claim 1, further comprising a video compositor for receiving the blended graphics and a video, and for blending the blended graphics and the video using the at least one blending factor to generate a displayable image.

10. The video and graphics system of claim 9, the graphics converters, the graphics controller, the graphics blenders, and the video compositor are implemented on a single integrated circuit chip.

11. A method of blending a plurality of graphics data portions to generate a blended graphics image using a video and graphics system comprising a plurality of graphics converters, a graphics controller and a plurality of graphics blenders implemented on a single integrated circuit chip, the method comprising:

converting the graphics data portions to a plurality of converted graphics data portions using the graphics converters;

ordering the converted graphics data portions into an order suitable for blending using the graphics controller; and

generating the blended graphics image by concurrently blending the converted graphics data portions using the graphics blenders.

12. The method of claim 11, wherein the plurality of graphics data portions comprise a plurality of graphics windows.

13. The method of claim 11, wherein generating the blended graphics image comprises blending at least two of the converted graphics data portions to generate a first one of intermediate graphics images, blending at least two other ones of the converted graphics data portions to generate a second one of the intermediate graphics images, and blending the intermediate graphics images to generate the blended graphics image.

14. The method of claim 13, wherein blending at least two of the converted graphics data portions comprises blending at least two upper layer data portions, and blending at least two other ones of the converted graphics data portions comprises blending at least two lower layer data portions, wherein the at least two upper layer data portions are blended concurrently with the blending of the at least two lower layer data portions.

15. The method of claim 11, wherein converting the graphics data portions comprises generating a plurality of converted graphics data portions having a common format.

16. The method of claim 11, wherein converting the graphics data portions comprises converting the graphics data portions having a CLUT data format using a plurality of CLUTs, each of the CLUTs corresponding to one of the graphics converters.

17. The method of claim 11, wherein each of the converted graphics data portions represents a plurality of pixels and at least one blending factor, wherein generating the blended graphics image comprises concurrently blending the converted graphics data portions using the at least one blending factor.

18. The method of claim 11, further comprising blending the blended graphics image and a video using at least one blending factor in a video compositor implemented on the single integrated circuit chip.

19. A video and graphics system comprising:

conversion means for receiving the graphics data portions, and converting the graphics data portions to generate converted graphics data portions;

ordering means for receiving the converted graphics data portions and ordering the converted graphics data portions into an order suitable for blending; and

blending means for blending the converted graphics data portions concurrently to generate a blended graphics image.

20. The video and graphics system of claim 19, further comprising compositing means for blending the blended graphics image with a video to generate a displayable image.