API communications for vertex and pixel shaders

• US 7,659,902 B2
• Filed: 06/26/2006
• Issued: 02/09/2010
• Est. Priority Date: 03/07/2000
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Toelle, Michael A., Boyd, Charles N.
• Primary Examiner(s): Nguyen; Hau H
• Application Number:
  US11/426,485
• Publication Number:
  US 20060244753A1
• Time in Patent Office: 1,324 Days
• Field of Search: 345/559, 345/561, 345/538, 345/426, 345/522, 345/519, 345/501, 345/537, 709/328
• US Class Current: 345/522
• CPC Class Codes: G06T 15/00 3D [Three Dimensional] image rendering
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 15/80 Shading
• CPC Class Codes: G06T 2210/32 Image data format

Abstract

A three-dimensional API for communicating with hardware implementations of vertex shaders and pixel shaders having local registers. With respect to vertex shaders, API communications are provided that may make use of an on-chip register index and API communications are also provided for a specialized function, implemented on-chip at a register level, that outputs the fractional portion(s) of input(s). With respect to pixel shaders, API communications are provided for a specialized function, implemented on-chip at a register level, that performs a linear interpolation function and API communications are provided for specialized modifiers, also implemented on-chip at a register level, that perform modification functions including negating, complementing, remapping, stick biasing, scaling and saturating. Advantageously, these API communications expose these very useful on-chip graphical algorithmic elements to a developer while hiding the details of the operation of the vertex shader and pixel shader chips from the developer.

Claims

1. A computing system for communicating between a 3-D graphics API of a host computing system having a main memory stack and a 3-D graphics hardware rendering device having on-chip register storage, comprising:

means for receiving at least one instruction having at least one graphics data argument by the 3-D graphics API of the host computing system;

means for formatting said at least one instruction for the register storage of the hardware rendering device;

means for providing said at least one formatted instruction to the hardware rendering device;

means for processing said at least one graphics data argument, pursuant to said at least one formatted instruction, by the hardware rendering device; and

means for outputting the result of said processed at least one graphics data argument by the means for processing from said hardware rendering device in accordance with said at least one formatted instruction.

2. The computing system of claim 1, further comprising means for storing a register index in the on-chip register storage.

3. The computing system of claim 1, wherein said at least one instruction is an instruction with at least one floating point number argument and said means for outputting includes means for outputting from the hardware rendering device a fractional portion of said at least one floating point number argument.

4. The computing system of claim 1, wherein said at least one instruction is an instruction with a plurality of floating point number arguments and said means for processing includes means for processing the plurality of floating point number arguments to calculate a number representative of a linear interpolation between two of the floating point number arguments.

5. The computing system of claim 1, wherein said at least one instruction is an instruction with a plurality of floating point number arguments and said means for outputting includes means for outputting a floating point number representative of a linear interpolation between two of the floating point number arguments.

6. The computing system of claim 1, wherein said at least one instruction includes a special modifier function to be performed during said processing of the graphics data by means for processing of the hardware rendering device, the special modifier function including at least one of a negating modifier, complementing modifier, remapping modifier, stick biasing modifier, saturating modifier and scaling modifier.

7. A computer-readable storage medium bearing computer executable instructions for communicating between a 3-D graphics API of a host computing system having a main memory stack and a hardware procedural shader having on-chip register storage, comprising:

means for receiving at least one instruction having at least one graphics data argument by the 3-D API of the host computing system;

means for formatting said at least one instruction for use with the hardware procedural shader;

means for providing said at least one formatted instruction to said hardware procedural shader;

means for processing said at least one graphics data argument, pursuant to said at least one formatted instruction, by the hardware procedural shader; and

means for outputting the result of said processed at least one graphics data argument from said hardware procedural shader in accordance with said at least one formatted instruction.

8. The computer readable storage medium of claim 7, further comprising means for storing a register index in the on-chip register storage of the procedural shader, wherein the procedural shader is a vertex shader.

9. The computer readable storage medium of claim 8, further comprising means for accessing the register index stored in the on-chip register storage and finding another register of the on-chip register storage to be used incident to carrying out said at least one instruction by said hardware vertex shader.

10. The computer readable storage medium of claim 7, wherein the procedural shader is a vertex shader, and wherein said at least one instruction is an instruction with at least one floating point number argument and said means for outputting includes means for outputting from the vertex shader a fractional portion of said at least one floating point number argument.

11. The computer readable storage medium of claim 7, wherein the procedural shader is a pixel shader, and wherein said at least one instruction is an instruction with a plurality of floating point number arguments and said means for processing includes means for processing the plurality of floating point number arguments to calculate a number representative of a linear interpolation between two of the floating point number arguments.

12. The computer readable storage medium of claim 7, wherein the procedural shader is a pixel shader, and said at least one instruction is an instruction with a plurality of floating point number arguments and said means for outputting includes means for outputting a floating point number representative of a linear interpolation between two of the floating point number arguments.

13. The computer readable storage medium of claim 7, wherein the procedural shader is a pixel shader, and wherein said at least one instruction includes a special modifier function to be performed during said processing by the means for processing of the graphics data by an arithmetic/logic unit of the pixel shader.

14. The computer readable storage medium of claim 13, wherein said special modifier function performed during said processing by said means for processing is at least one of a negating modifier, complementing modifier, remapping modifier, stick biasing modifier, saturating modifier and scaling modifier.

15. A computing device comprising the computer-readable storage medium of claim 7.

16. A computer system, comprising:

hardware rendering means for rendering graphics data having on-chip register storage means;

a host computing system having stored thereon interface means for communicating at least one instruction having at least one graphics data argument formatted for the on-chip register storage means of said hardware rendering means to said hardware rendering means;

wherein said hardware rendering means receives said at least one instruction; and

wherein the hardware rendering means processes said at least one graphics data argument incident to the performance of said at least on instruction and said hardware rendering means outputs the result of the processing.

17. The computer system of claim 16, wherein said at least one graphics data argument is formatted to be remapped to a register state of the on-chip register storage means.

18. The computer system of claim 16, wherein said at least one instruction is communicated directly to said hardware rendering means, bypassing a main memory stack of the host computing system.

19. The computer system of claim 16, wherein incident to the processing of said at least one graphics data argument, the hardware rendering means performs at least one of reading from and writing to the on-chip register storage means.

20. The computer system of claim 16, wherein said hardware rendering means further comprises a register index stored in the on-chip register storage means.