Programming method to reduce gate coupling interference for non-volatile memory

• US 7,660,158 B2
• Filed: 06/19/2008
• Issued: 02/09/2010
• Est. Priority Date: 02/16/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Aritome, Seiichi
• Primary Examiner(s): Auduong; Gene N.
• Application Number:
  US12/142,293
• Publication Number:
  US 20080253188A1
• Time in Patent Office: 600 Days
• Field of Search: 365/185.17, 365/185.03, 365/185.18, 365/185.23, 365/185.24
• US Class Current: 365/185.17
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/0491 Virtual ground arrays
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification
• CPC Class Codes: G11C 2211/5642 Multilevel memory with buffers, latches, registers at input or output
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory

Abstract

A non-volatile memory device and programming process is described that compensates for coupling effects on threshold gate voltages of adjacent floating gate or non-conductive floating node memory cells by adjusting the threshold voltage level programmed in view of the data being programmed on a following programming cycle into adjacent memory cells, so that the coupling effect results in the desired target threshold voltages for the cells. In one embodiment of the present invention, memory cell coupling is compensated for by adjusting programming level of one or more memory cells of a first page a memory array to a higher or lower threshold verify target voltage given the data/programming level to be written to directly adjacent memory cells of a second page, so that coupling between the directly adjacent memory cells of the first and second pages brings the memory cells of first page to their final target programming level.

Claims

1. A method of programming non-volatile memory cells of a non-volatile memory array, comprising:

receiving first write data and second write data; and

adjusting the programming of the first write data into a first plurality of memory cells of a non-volatile memory array to compensate for interference by the subsequent programming of the second write data into a second plurality of memory cells of the non-volatile memory array, wherein the memory cells of the first plurality are physically adjacent the memory cells of the second plurality in the non-volatile memory array.

2. The method of claim 1, further comprising:

programming the compensated first write data into the first plurality of memory cells of the non-volatile memory array; and

programming the second write data into the second plurality of memory cells of the non-volatile memory array.

3. The method of claim 1, wherein adjusting the programming of the first write data further comprises selectively adjusting a target threshold voltage to be programmed into one or more memory cells of the first plurality of memory cells of the non-volatile memory array.

4. The method of claim 3, wherein adjusting the programming of the first write data further comprises selectively adjusting one or more memory cells of the first plurality of memory cells of the non-volatile memory array to a lower erased state threshold voltage during erasure.

5. The method of claim 1, further comprising:

receiving third write data; and

adjusting the programming of the second write data into the second plurality of memory cells of the non-volatile memory array to compensate for interference by the subsequent programming of the third write data into a third plurality of memory cells of the non-volatile memory array.

6. The method of claim 5, further comprising:

programming the compensated first write data into the first plurality of memory cells of the non-volatile memory array; and

programming the compensated second write data into the second plurality of memory cells of the non-volatile memory array.

7. The method of claim 6, further comprising:

programming the third write data into the third plurality of memory cells of the non-volatile memory array.

8. The method of claim 1, wherein programming non-volatile memory cells of the non-volatile memory array comprises programming non-volatile memory cells of a memory array selected from the group consisting of a NAND architecture memory array, a NOR architecture memory array, an AND architecture memory array, and a virtual ground architecture memory array.

9. The method of claim 1, wherein adjusting the programming of the first write data into the first plurality of memory cells of the non-volatile memory array to compensate for interference by the subsequent programming of the second write data into the second plurality of memory cells of the array comprises adjusting the programming of the first write data into a first plurality of memory cells of a non-volatile memory array to compensate for interference by the subsequent programming of the second write data into a second plurality of memory cells of the array where each memory cell of the first plurality of memory cells is directly adjacent a memory cell of the second plurality of memory cells.

10. The method of claim 1, wherein adjusting the programming of the first write data into the first plurality of memory cells of the non-volatile memory array to compensate for interference by the subsequent programming of the second write data into the second plurality of memory cells of the array comprises adjusting the programming of the first write data into a first page of memory cells of a row of the non-volatile memory array to compensate for interference by the subsequent programming of the second write data into a second page of memory cells of the row of the non-volatile memory array, where the non-volatile memory array is arranged in rows and columns and each row of the array contains two or more pages of memory cells.

11. The method of claim 10, further comprising:

addressing the two or more pages of each row of the non-volatile memory array such that each memory cell of a page being programmed is directly adjacent a memory cell of a subsequently addressed page.

12. The method of claim 11, wherein the memory cells of the pages are programmed so as to trace an “

S”

pattern in the rows and columns of the non-volatile memory array.

13. The method of claim 1, wherein programming non-volatile memory cells of the non-volatile memory array comprises programming non-volatile memory cells of a type selected from the group consisting of floating gate memory cells, floating node memory cells, multi-level memory cells (MLCs), and non-conductive floating node memory cells with multiple charge storage centroids.

14. A method of programming non-volatile memory cells of a NAND architecture memory array having a plurality of NAND architecture memory strings, comprising:

receiving first write data and second write data;

selecting a first plurality of non-volatile memory cells from a plurality of the NAND architecture memory strings; and

adjusting the programming of the first write data into the first plurality of non-volatile memory cells to compensate for interference by the subsequent programming of the second write data into a second plurality of non-volatile memory cells of the plurality of the NAND architecture memory strings;

wherein each non-volatile memory cell of the first plurality of non-volatile memory cells is directly adjacent a non-volatile memory cell of the second plurality of non-volatile memory cells.

15. The method of claim 14, further comprising:

programming the compensated first write data into the first plurality of non-volatile memory cells; and

programming the second write data into the second plurality of non-volatile memory cells.

16. The method of claim 14, wherein adjusting the programming of the first write data further comprises selectively adjusting a target threshold voltage to be programmed into one or more non-volatile memory cells of the first plurality of non-volatile memory cells.

17. The method of claim 14, wherein programming the compensated first write data into the first plurality of non-volatile memory cells and programming the second write data into the second plurality of non-volatile memory cells comprises programming the compensated first write data into a first page of a row of non-volatile memory cells and programming the second write data into a second page of the row of non-volatile memory cells, wherein the non-volatile memory cells of the NAND architecture non-volatile memory array are arranged in rows and columns, wherein each row contains two or more pages of non-volatile memory cells.

18. The method of claim 17, wherein programming the compensated first write data into the first page of the row of non-volatile memory cells and programming the second write data into the second page of the row of non-volatile memory cells comprises programming the compensated first write data into the first page of the row of non-volatile memory cells and programming the second write data into the second page of the row of non-volatile memory cells where each page of the row is arranged such that each non-volatile memory cell of the first page of the row of non-volatile memory cells is directly adjacent a non-volatile memory cell of the subsequently addressed page of non-volatile memory cells of the row of non-volatile memory cells.

19. The method of claim 17, further comprising:

addressing the two or more pages of each row of the NAND architecture memory array such that each non-volatile memory cell of a page being programmed is directly adjacent a non-volatile memory cell of a subsequently addressed page.

20. The method of claim 14, wherein programming non-volatile memory cells of the NAND architecture memory array comprises programming non-volatile memory cells of a type selected from the group consisting of floating gate memory cells, floating node memory cells, multi-level memory cells (MLCs), and non-conductive floating node memory cells with multiple charge storage centroids.