Integrated flash memory systems and methods for load compensation

• US 7,660,161 B2
• Filed: 01/19/2007
• Issued: 02/09/2010
• Est. Priority Date: 01/19/2007
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Van Tran, Hieu
• Primary Examiner(s): Nguyen; Tuan T
• Assistant Examiner(s): LE, TOAN K
• Application Number:
  US11/655,901
• Publication Number:
  US 20080175062A1
• Time in Patent Office: 1,117 Days
• Field of Search: 365/205, 365/207, 365/210.1, 365/210.11, 365/185.03, 365/185.21, 365/189.06
• US Class Current: 365/185.21
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

Systems and methods are disclosed including features that compensate for variations in the magnitude of supply voltages used in memory arrays. According to some aspects, compensation circuits may provide a tunable current-limiting load for data columns, where the load can be tuned to dynamically compensate for variations in supply voltage. In certain aspects, a compensation circuit may employ an operational amplifier configured as a voltage follower. The voltage follower compensates for any variations in supply voltage, forcing a constant voltage drop across the load element(s), thus maintaining a constant load. Other circuits may also be included, such as precharge circuits, clamp circuits, buffer circuits, trimming circuit, and sense amplifier circuits with sensed body effect. System-On-Chip integrated system aspects may include a microcontroller, a mixed IP, and a flash memory system having functionality and blocks that interface and interoperate with each other for load compensation.

Claims

1. A multilevel memory system configured to detect a voltage level stored in a multilevel memory cell, comprising:

a memory sensing circuit connected to the multilevel memory cell and having a voltage supply terminal,

a load element connected between the voltage supply terminal and the multilevel memory cell, the load element providing a load for the memory sensing circuit as a function of a voltage drop across at least a portion of the load element and a current through the load element; and

a load compensation circuit connected to the load element and configured to maintain the load by compensating for a load variation of the load;

wherein the load element includes a PMOS transistor;

wherein the load compensation circuit is configured as a voltage follower circuit configured to maintain the load by maintaining a voltage drop across a portion of the PMOS transistor; and

wherein the voltage follower circuit comprises;

an operational amplifier having a non inverting terminal, an inverting terminal, and an output terminal, the output terminal connected to a gate terminal of the PMOS transistor, and the noninverting terminal connected to a drain terminal of the PMOS transistor, so as to maintain the voltage drop between the drain terminal of the PMOS transistor and the source terminal of the PMOS transistor;

a voltage source configured to maintain a voltage at the inverting terminal; and

a current source configured to maintain a current through the PMOS transistor.

2. The system of claim 1 wherein the load element includes an enhancement PMOS transistor, a native PMOS transistor, a slightly depleted PMOS transistor, or a MOS transistor.

3. The system of claim 1 wherein the load variation is a load variation due to at least one of a variation in a magnitude of a voltage applied at the voltage supply terminal, a variation in a temperature of the load element, or a variation in a fabrication of the load element.

4. The system of claim 1 wherein the load compensation circuit is further configured to maintain the load at a predetermined value.

5. The system of claim 1 wherein the memory system is non-volatile.

6. A multilevel memory system configured to detect a voltage level stored in a multilevel memory cell, comprising:

a memory sensing circuit connected to the multilevel memory cell and having a voltage supply terminal,

a load element connected between the voltage supply terminal and the multilevel memory cell, the load element providing a load for the memory sensing circuit as a function of a voltage drop across at least a portion of the load element and a current through the load element; and

a load compensation circuit connected to the load element and configured to maintain the load by compensating for a load variation of the load;

wherein the load element includes a PMOS transistor;

wherein the load compensation circuit is configured as a voltage follower circuit configured to maintain the load by maintaining a voltage drop across a portion of the PMOS transistor; and

wherein the voltage follower circuit comprises;

an operational amplifier having a noninverting terminal, an inverting terminal, and an output terminal, the output terminal connected to a gate terminal of the PMOS transistor, and the noninverting terminal connected to a drain terminal of the PMOS transistor, so as to maintain the voltage drop between the drain terminal of the PMOS transistor and the source terminal of the PMOS transistor;

a resistor connected between a voltage source terminal and the inverting terminal of the operational amplifier; and

a current mirror connected between the inverting terminal of the operational amplifier and the drain terminal of the PMOS transistor, and configured to mirror the current through the PMOS transistor as a second current through the resistor.

7. The system of claim 6 wherein the load element includes an enhancement PMOS transistor, a native PMOS transistor, a slightly depleted PMOS transistor, or a MOS transistor.

8. The system of claim 6 wherein the load variation is a load variation due to at least one of a variation in a magnitude of a voltage applied at the voltage supply terminal, a variation in a temperature of the load element, or a variation in a fabrication of the load element.

9. The system of claim 6 wherein the load compensation circuit is further configured to maintain the load at a predetermined value.

10. The system of claim 6 wherein the memory system is non-volatile.

11. A multilevel memory system configured to detect a voltage level stored in a multilevel memory cell, comprising:

a memory sensing circuit connected to the multilevel memory cell and having a voltage supply terminal,

a load element connected between the voltage supply terminal and the multilevel memory cell, the load element providing a load for the memory sensing circuit as a function of a voltage drop across at least a portion of the load element and a current through the load element; and

a load compensation circuit connected to the load element and configured to maintain the load by compensating for a load variation of the load;

wherein the load element includes a PMOS transistor;

wherein the load compensation circuit is configured as a voltage follower circuit configured to maintain the load by maintaining a voltage drop across a portion of the PMOS transistor; and

wherein the voltage follower circuit further comprises;

an operational amplifier having a noninverting terminal, an inverting terminal, and an output terminal, the output terminal connected to a gate terminal of the PMOS transistor, and the noninverting terminal connected to a drain terminal of the PMOS transistor, so as to maintain the voltage drop between the drain terminal of the PMOS transistor and the source terminal of the PMOS transistor;

a resistor connected between a voltage source terminal and the inverting terminal of the operational amplifier;

a first current source configured to transmit the current through the PMOS transistor; and

a second current source configured to transmit a second current through the resistor, the second current having a magnitude approximately equal to a magnitude of the current through the PMOS transistor.

12. The system of claim 11 wherein the resistor has an adjustable resistance, the resistor configured to compensate for the load variation by adjusting a voltage at the inverting terminal according to the adjustable resistance.

13. The system of claim 11 wherein the load element includes an enhancement PMOS transistor, a native PMOS transistor, a slightly depleted PMOS transistor, or a MOS transistor.

14. The system of claim 11 wherein the load variation is a load variation due to at least one of a variation in a magnitude of a voltage applied at the voltage supply terminal, a variation in a temperature of the load element, or a variation in a fabrication of the load element.

15. The system of claim 11 wherein the load compensation circuit is further configured to maintain the load at a predetermined value.

16. A multilevel memory system configured to detect a voltage level stored in a multilevel memory cell, comprising:

a memory sensing circuit connected to the multilevel memory cell and having a voltage supply terminal,

a load element connected between the voltage supply terminal and the multilevel memory cell, the load element providing a load for the memory sensing circuit as a function of a voltage drop across at least a portion of the load element and a current through the load element;

a load compensation circuit connected to the load element and configured to maintain the load by compensating for a load variation of the load; and

a precharge circuit in electrical communication with the memory sensing circuit, the precharge circuit configured to transmit a precharge to the memory sensing circuit so as to reduce a settle time of the memory sensing circuit.

17. The system of claim 16 wherein the precharge circuit further comprises a plurality of resistors configured in electrical series so as to transmit the precharge according to a ratio of the resistances of the resistors.

18. The system of claim 16 wherein the load element includes an enhancement PMOS transistor.

19. The system of claim 16 wherein the load element includes a native PMOS transistor.

20. The system of claim 16 wherein the load element includes a slightly depleted PMOS transistor.

21. The system of claim 16 wherein the load variation is a load variation due to at least one of a variation in a magnitude of a voltage applied at the voltage supply terminal, a variation in a temperature of the load element, or a variation in a fabrication of the load element.

22. The system of claim 16 wherein the load compensation circuit is further configured to maintain the load at a predetermined value.

23. The system of claim 16 wherein the load element includes a PMOS transistor.

24. The system of claim 23 wherein the load compensation circuit is configured as a voltage follower circuit configured to maintain the load by maintaining a voltage drop across a portion of the PMOS transistor.

25. The system of claim 16 wherein the memory system is non-volatile.

26. A multilevel memory system configured to detect a voltage level stored in a multilevel memory cell, comprising:

a memory sensing circuit connected to the multilevel memory cell and having a voltage supply terminal,

a load element connected between the voltage supply terminal and the multilevel memory cell, the load element providing a load for the memory sensing circuit as a function of a voltage drop across at least a portion of the load element and a current through the load element;

a load compensation circuit connected to the load element and configured to maintain the load by compensating for a load variation of the load; and

a clamp circuit in electrical communication with the memory sensing circuit, the clamp circuit configured to apply a clamp voltage to the memory sensing circuit so as to maintain a voltage within the memory sensing circuit.

27. The system of claim 26 wherein the clamp circuit further includes a voltage source terminal and a PMOS transistor coupled between the voltage source terminal and the multilevel memory cell.

28. The system of claim 26 wherein the memory sensing circuit is configured to generate an output voltage signal corresponding to data stored in the multilevel memory cell, the output voltage having an associated noise, the system further comprising:

a buffer circuit having an input terminal connected to the memory sensing circuit and configured to receive the output voltage signal, and having an output terminal, the buffer circuit configured to decouple the output voltage signal from the associated noise so as to form a decoupled output voltage signal, and configured to transmit the decoupled output voltage signal at the output terminal.

29. The system of claim 28 wherein the buffer circuit further includes a voltage source terminal and a native NMOS transistor having a gate terminal connected to the input terminal, a drain terminal connected to the voltage source terminal, and a source terminal connected to the output terminal.

30. The system of claim 29 wherein the buffer circuit further includes a trimming circuit in electrical communication with the output terminal, the trimming circuit configured to trim the decoupled output voltage signal.

31. The system of claim 30 wherein the trimming circuit includes a trimming circuit transistor having a drain terminal in electrical communication with the output terminal and having a grounded source terminal.

32. The system of claim 31 wherein the trimming circuit further includes at least one resistor connected between the output terminal and a ground terminal.

33. The system of claim 31 wherein the trimming circuit further includes at least one resistor connected between the output terminal and the trimming circuit transistor.

34. The system of claim 31 wherein the trimming circuit further includes a plurality of trimming circuit transistors each having a drain terminal in electrical communication with the output terminal and having a grounded source terminal.

35. The system of claim 28:

wherein the buffer circuit further includes a voltage source terminal and a plurality of buffer circuit transistors each having a gate terminal connected to the input terminal, a drain terminal connected to the voltage source terminal, and a source terminal connected to the output terminal; and

wherein the buffer circuit further includes a trimming transistor having a drain terminal in electrical communication with the output terminal and having a grounded source terminal, the trimming transistor configured to trim the decoupled output voltage signal.

36. The system of claim 26 wherein the clamp circuit further includes a voltage source terminal and an NMOS transistor coupled between the voltage source terminal and the multilevel memory cell.

37. The system of claim 26 wherein the load element includes an enhancement PMOS transistor.

38. The system of claim 26 wherein the load element includes a native PMOS transistor.

39. The system of claim 26 wherein the load element includes a slightly depleted PMOS transistor.

40. The system of claim 26 wherein the load variation is a load variation due to at least one of a variation in a magnitude of a voltage applied at the voltage supply terminal, a variation in a temperature of the load element, or a variation in a fabrication of the load element.

41. The system of claim 26 wherein the load compensation circuit is further configured to maintain the load at a predetermined value.

42. The system of claim 26 wherein the load element includes a PMOS transistor.

43. The system of claim 42 wherein the load compensation circuit is configured as a voltage follower circuit configured to maintain the load by maintaining a voltage drop across a portion of the PMOS transistor.

44. The system of claim 26 wherein the memory system is non-volatile.

45. A multilevel memory system configured to detect a voltage level stored in a multilevel memory cell, comprising:

a memory sensing circuit connected to the multilevel memory cell and having a voltage supply terminal,

a load element connected between the voltage supply terminal and the multilevel memory cell, the load element providing a load for the memory sensing circuit as a function of a voltage drop across at least a portion of the load element and a current through the load element; and

a load compensation circuit connected to the load element and configured to maintain the load by compensating for a load variation of the load;

wherein the load compensation circuit further comprises at least one resistor having an adjustable resistance, the at least one resistor connected to a tuned element so as to compensate for the load variation by adjusting the current through the load element according to the adjustable resistance.

46. The system of claim 45 wherein the load element includes an enhancement PMOS transistor.

47. The system of claim 45 wherein the load element includes a native PMOS transistor.

48. The system of claim 45 wherein the load element includes a slightly depleted PMOS transistor.

49. The system of claim 45 wherein the load variation is a load variation due to at least one of a variation in a magnitude of a voltage applied at the voltage supply terminal, a variation in a temperature of the load element, or a variation in a fabrication of the load element.

50. The system of claim 45 wherein the load compensation circuit is further configured to maintain the load at a predetermined value.

51. The system of claim 45 wherein the load element includes a PMOS transistor.

52. The system of claim 51 wherein the load compensation circuit is configured as a voltage follower circuit configured to maintain the load by maintaining a voltage drop across a portion of the PMOS transistor.

53. The system of claim 45 wherein the memory system is non-volatile.

54. A multilevel memory system configured to detect a voltage level stored in a multilevel memory cell, comprising:

a memory sensing circuit connected to the multilevel memory cell and having a voltage supply terminal,

a load element connected between the voltage supply terminal and the multilevel memory cell, the load element providing a load for the memory sensing circuit as a function of a voltage drop across at least a portion of the load element and a current through the load element; and

a load compensation circuit connected to the load element and configured to maintain the load by compensating for a load variation of the load;

wherein the load element includes a first transistor having a drain terminal and a gate terminal, the transistor configured to operate in a saturation mode according to a voltage applied between the drain terminal and the gate terminal, and wherein the load compensation circuit further comprises a voltage source connected between the gate terminal and the drain terminal and configured to apply the voltage between the gate terminal and the drain terminal so as to render the first transistor operable in the saturation mode.

55. The system of claim 54 wherein the voltage source further comprises:

a second transistor having a gate terminal connected to the drain terminal of the first transistor, and a source terminal connected to the gate terminal of the first terminal, and a grounded drain terminal; and

a current source connected to the source terminal.

56. The system of claim 54 wherein the voltage source further comprises a resistor and a current source in electrical series, the resistor connected between the drain terminal and the gate terminal, and the current source connected between the gate terminal and a ground terminal.

57. The system of claim 54 wherein the voltage source further comprises a first resistor and a second resistor in electrical series, the first resistor connected between the drain terminal and the gate terminal, and the second resistor connected between the gate terminal and a ground terminal.

58. The system of claim 54 wherein the load element includes an enhancement PMOS transistor.

59. The system of claim 54 wherein the load element includes a native PMOS transistor.

60. The system of claim 54 wherein the load element includes a slightly depleted PMOS transistor.

61. The system of claim 54 wherein the load variation is a load variation due to at least one of a variation in a magnitude of a voltage applied at the voltage supply terminal, a variation in a temperature of the load element, or a variation in a fabrication of the load element.

62. The system of claim 54 wherein the load compensation circuit is further configured to maintain the load at a predetermined value.

63. The system of claim 54 wherein the load element includes a PMOS transistor.

64. The system of claim 63 wherein the load compensation circuit is configured as a voltage follower circuit configured to maintain the load by maintaining a voltage drop across a portion of the PMOS transistor.

65. The system of claim 54 wherein the memory system is non-volatile.