Low power memory device

• US 7,660,183 B2
• Filed: 08/01/2005
• Issued: 02/09/2010
• Est. Priority Date: 08/01/2005
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Tsern, Ely K., Hampel, Craig E., Ware, Frederick A.
• Primary Examiner(s): Ho; Hoai V
• Assistant Examiner(s): TRAN, ANTHAN
• Application Number:
  US11/194,812
• Publication Number:
  US 20070028060A1
• Time in Patent Office: 1,653 Days
• Field of Search: 365/230.03
• US Class Current: 365/230.03
• CPC Class Codes: G11C 11/4063 Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 5/14 Power supply arrangements , e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

In a memory device having a memory core and a signal interface, receiving a command that specifies at least a portion of a memory access. During the memory access, transferring data between the memory core and the signaling interface, and transferring the data between the signaling interface and an external signal path, and prior to transferring the data between the signaling interface and the external signal path, receiving enable information to selectively enable at least a first memory resource and a second memory resource, wherein each of the first memory resource and the second memory resource performs a control function associated with the memory access.

Claims

1. A method of operation within a memory device, the method comprising:

receiving address information and corresponding enable information in association with a memory access request, wherein the address information includes a row address that specifies a row of storage cells within a storage array of the memory device, and a column address that corresponds to a column of storage cells within the specified row of storage cells, and wherein the enable information includes a first enable value that corresponds to a first storage location formed by a first subset of the column of storage cells, and a second enable value that corresponds to a second storage location formed by a second subset of the column of storage cells; and

selectively transferring data from the first and second storage locations to a bank of sense amplifiers according to states of the first and second enable values, including transferring data from the first storage location to the bank of sense amplifiers if the first enable value is in an enable state and transferring data from the second storage location to the bank of sense amplifiers if the second enable value is in the enable state.

2. The method of claim 1 further comprising selectively enabling write drivers to output write data to the bank of sense amplifiers according to the states of the enable values, wherein selectively enabling write drivers to output write data to the bank of sense amplifiers according to the states of the enable values comprises selectively enabling write drivers to output write data to address-specified columns of sense amplifiers within the bank of sense amplifiers.

3. The method of claim 1 wherein selectively transferring data from the first and second storage locations to the bank of sense amplifiers comprises selectively asserting activate-enable signals that correspond to respective subbanks of the storage bank, each of the activate-enable signals being asserted or deasserted according to whether the enable information indicates that at least one storage location to be accessed is disposed within the sub-bank to which the activate-enable signal corresponds.

4. The method of claim 3 wherein the specified row of storage cells comprises subrows of storage cells disposed, respectively, in the subbanks of the storage bank, and wherein selectively transferring data from the first and second storage locations to the bank of sense amplifiers further comprises, for each of the subbanks, transferring data from the subrow of storage cells within the subbank to sense amplifiers of the subbank if the corresponding activate-enable signal is asserted, and wherein the sense amplifiers of each of the subbanks constitute a respective portion of the bank of sense amplifiers.

5. The method of claim 4 wherein transferring data from the subrow of storage cells within the subbank to sense amplifiers of the subbank if the activate-enable signal is asserted comprises activating a word line coupled to the subrow of storage cells within the subbank if the activate-enable signal is asserted.

6. The method of claim 4 wherein transferring data from the subrow of storage cells within the subbank to sense amplifiers of the subbank if the corresponding activate-enable signal is asserted comprises activating a sense line coupled to the sense amplifiers of the subbank.

7. The method of claim 1 wherein receiving address information in association with a memory access request comprises receiving the row address and column address at different times and in association with respective operation codes.

8. A method of operation within a memory device having a plurality of storage banks, the method comprising:

receiving, in association with a memory access request, a row address that corresponds to a range of storage locations within the memory device, a column address that corresponds to a group of storage locations within the range of storage locations and enable values that correspond to respective storage locations within the group of storage locations, including receiving a first enable value that corresponds to a first storage location and a second enable value that corresponds to a second storage location; and

selectively transferring read data from the group of storage locations to an external signaling interface of the memory device according to states of the enable values, including transferring first read data from the first storage location to the external signaling interface if the first enable value is in an enable state and transferring second read data from the second storage location to the external signaling interface if the second enable value is in the enable state.

9. The method of claim 8 wherein selectively transferring read data from the storage locations to an external signaling interface comprises selectively transferring the read data from the storage locations to a sense amplifier bank according to the states of the enable values.

10. The method of claim 8 wherein selectively transferring read data from the storage locations to the external signaling interface comprises selectively transferring the read data from a sense amplifier bank of the memory device to the external signaling interface according to the states of the enable signals.

11. The method of claim 10 wherein selectively transferring the read data from the sense amplifier bank to the external signaling interface comprises selectively loading the read data into output storage circuits according to the states of the enable signals.

12. The method of claim 10 wherein selectively transferring the read data from the sense amplifier bank to the external signaling interface comprises selectively enabling output drivers to output the read data to the external signaling interface according to the states of the enable signals.

13. A memory device comprising:

a storage bank having a plurality of storage subbanks;

a sense amplifier bank having a plurality of sense amplifier subgroups coupled respectively to the storage subbanks;

interface circuitry to receive, in connection with a memory access request, (i) a row address that corresponds to a range of storage locations within the storage bank, (ii) a column address that corresponds to a subset of storage locations within the range of storage locations and (iii) enable values that correspond to respective storage locations within the subset of storage locations, wherein each enable value indicates whether the corresponding storage location is to be accessed in response to the memory access request; and

control circuitry to selectively enable data to be transferred from the storage subbanks to the sense amplifier subgroups according to the enable values.

14. The memory device of claim 13 wherein the range of storage locations comprises storage locations disposed within each of the storage subbanks and wherein the control circuitry comprises circuitry to enable data to be transferred, for each of the storage subbanks indicated by the enable values to contain at least one of the storage locations to be accessed, from the storage subbank to the respective sense amplifier subgroup.

15. The memory device of claim 14 wherein the circuitry to enable data to be transferred from the storage subbank to the respective sense amplifier subgroup comprises circuitry to activate a word line coupled to a row of storage cells within the subbank if the enable values indicate that the storage subbank contains at least one of the storage locations to be accessed.

16. The memory device of claim 14 wherein the circuitry to enable data to be transferred from the storage subbank to the respective sense amplifier subgroup comprises circuitry to activate a sense line coupled to the sense amplifier subgroup if the enable values indicate that the storage subbank coupled to the sense amplifier subgroup contains at least one of the storage locations to be accessed.

17. The memory device of claim 13 further comprising write driver circuitry to selectively output write data to the sense amplifier groups according to the enable values.

18. The memory device of claim 13 wherein the interface circuitry comprises circuitry to receive the row address and column address at different times and in association with respective operation codes.

19. A memory device comprising:

a sense amplifier bank having a plurality of sense amplifier subgroups;

interface circuitry to receive, in connection with a memory access request, (i) a row address value that corresponds to a range of storage locations within the memory device, (ii) a column address that corresponds to a subset of storage locations within the range of storage locations, and (iii) enable bits that correspond to respective storage locations within the subset of storage locations, wherein each enable bit indicates whether the corresponding storage location is to be accessed; and

a plurality of decoder circuits to form respective signal paths for accessing each of the sense amplifier subgroups indicated by the enable bits to contain data from at least one of the storage locations to be accessed.

20. The memory device of claim 19 further comprising an internal data path switchably coupled to the plurality of sense amplifier subgroups via the signal paths formed by the plurality of decoder circuits.

21. The memory device of claim 19 wherein each of the sense amplifier subgroups comprises a plurality of sense amplifiers, and wherein each of the decoder circuits comprises an output enable circuit to activate an output enable line coupled in common to the plurality of sense amplifiers within a corresponding one of the sense amplifier subgroups if the enable bits indicate that the one of the sense amplifier subgroups contains data from at least one of the storage locations to be accessed.

22. The memory device of claim 19 wherein each of the decoder circuits corresponds to a respective one of the sense amplifier subgroups and comprises a multiplexer to form a path between address-selected sense amplifiers within the corresponding sense amplifier subgroup and output nodes of the decoder circuit if the enable bits indicate that the sense amplifier subgroup contains data from at least one of the storage locations to be accessed.

23. The memory device of claim 19 further comprising write drivers coupled to the signal paths for accessing each of the sense amplifier subgroups.

24. The memory device of claim 23 further comprising control logic to selectively enable each of the write drivers to output write data to a respective address-selected column of sense amplifiers within the plurality of sense amplifier subgroups based, at least in part, on the state of a corresponding one of the enable bits.

25. The memory device of claim 23 further comprising a read pipeline register having storage circuits coupled respectively to the signal paths to receive read data from each of the sense amplifier subgroups.

26. The memory device of claim 25 further comprising control logic to selectively load each of the storage circuits of the read pipeline register with data from a respective address-selected column of sense amplifiers within the plurality of sense amplifier banks based, at least in part, on the state of a corresponding one of the enable bits.

27. The memory device of claim 19 wherein the interface circuitry comprises circuitry to receive the row address and column address at different times and in association with respective operation codes.

28. Computer-readable media having information embodied therein that includes a description of an integrated circuit device, the information including descriptions of:

a storage bank having a plurality of storage subbanks;

a sense amplifier bank having a plurality of sense amplifier subgroups coupled respectively to the storage subbanks;

interface circuitry to receive, in connection with a memory access request, (i) a row address value that corresponds to a range of storage locations within the storage bank, (ii) a column address that corresponds to a subset of storage locations within the range of storage locations, and (iii) enable bits that correspond to respective storage locations within the subset of storage locations, wherein each enable bit indicates whether the corresponding storage location is to be accessed; and

control circuitry to selectively enable data to be transferred from the storage subbanks to the sense amplifier subgroups according to the enable bits.