Combined matching and filter circuit

• US 7,660,562 B2
• Filed: 06/21/2004
• Issued: 02/09/2010
• Est. Priority Date: 06/21/2004
• Status: Active Grant

• Current Assignee: MACOM Technology Solutions Holdings, Inc.
• Original Assignee: MACOM Technology Solutions Holdings, Inc.
• Inventors: Weigand, Christopher Dirk, Jain, Nitin, Onno, Peter, Rajanish
• Primary Examiner(s): Jackson; Blane J
• Application Number:
  US10/872,947
• Publication Number:
  US 20050282503A1
• Time in Patent Office: 2,059 Days
• Field of Search: 455/80, 455/73, 455/307, 455/114.2, 455/129, 455/114.1, 333 32- 35, 333 24 R-143, 333202-212, 333/167, 333/175, 333/176, 333/184, 330/251, 330/286, 330/306
• US Class Current: 455/114.1
• CPC Class Codes: H03H 2001/0064 comprising semiconductor material
• CPC Class Codes: H03H 2001/0078 comprising spiral inductor on a substrate
• CPC Class Codes: H03H 7/0115 comprising only inductors and capacitors H03H7/075, H03H7/09, H03H7/12, H03H7/13 take precedence
• CPC Class Codes: H03H 7/0123 comprising distributed impedance elements together with lumped impedance elements
• CPC Class Codes: H03H 7/1758 Series LC in shunt or branch path H03H7/1791 takes precedence
• CPC Class Codes: H03H 7/1766 Parallel LC in series path H03H7/1783 takes precedence
• CPC Class Codes: H03H 7/1783 Combined LC in series path
• CPC Class Codes: H03H 7/1791 Combined LC in shunt or branch path
• CPC Class Codes: H03H 7/38 Impedance-matching networks

Abstract

A combined matching and harmonic rejection circuit with increased harmonic rejection provided by a split resonance for one or more of the capacitive or inductive elements of the circuit. At a fundamental frequency, the circuit comprises an inductive series arm with capacitive shunt arms. The capacitance of a shunt arm may be provided by two or more parallel paths, each having a capacitor and an inductor in series so that, in addition to providing the effective capacitance necessary for impedance matching at the fundamental frequency, two separate harmonics represented by the series resonances of the parallel paths are rejected. In this manner, an extra null in the circuit'"'"'s stop-band may be achieved using the same number of shunt elements necessary to achieve impedance matching at the fundamental frequency.

Claims

1. A method of combining impedance matching and harmonic rejection, comprising the steps of:

providing an impedance matching circuit at a fundamental frequency (F_o), said matching circuit comprising;

a first shunt arm having a first, impedance-matching-required, effective capacitance at said fundamental frequency, comprising, in parallel, a first shunt path having a first capacitor and a first inductor in series and a second shunt path having a second capacitor and a second inductor in series, providing rejection at a first harmonic frequency and at a second harmonic frequency;

a series arm comprising a first inductive element having a first, impedance-matching-required inductance at said fundamental frequency, and a third inductor and a third capacitor in parallel, wherein said third capacitor acts as an effective open circuit at said fundamental frequency but parallel resonates with said third inductor in the vicinity of a third harmonic frequency, thereby providing rejection of said third harmonic frequency; and

a second shunt arm located between said first inductive element and an output port of said impedance matching circuit, said second shunt arm comprising, in series, a fourth capacitor and a fourth inductor selected to have a second, impedance-matching-required capacitance at said fundamental frequency and harmonic rejection at a fourth harmonic frequency, wherein (i) said first shunt path provides harmonic rejection at said first harmonic frequency, (ii) said second shunt path provides harmonic rejection at said second harmonic frequency, and (iii) said first shunt path and said second shunt path in combination parallel resonate to an open circuit at a frequency substantially equal to a series resonance of said fourth capacitor and said fourth inductor in said second shunt arm.

2. The method of claim 1 further comprising the step of placing said third inductor and said fourth inductor in physical proximity to establish a mutual inductance between said third inductor and fourth inductor, said mutual inductance having a coefficient of mutual inductance of greater than 0.20, thereby reducing a required size of both said third and forth inductor.

3. The method as recited in claim 1 further comprising the step of fabricating said impedance matching circuit as a monolithic integrated circuit.

4. A combined impedance matching and harmonic rejection circuit, comprising:

a first shunt arm comprising, in parallel, a first shunt path and a second shunt path, and having a first, impedance-matching-required capacitance at a fundamental frequency (F_o), said first shunt path comprising a first capacitor and a first inductor in series, and having a series resonance at a first harmonic frequency, and said second shunt path comprising a second capacitor and a second inductor in series, and having a series resonance at a second harmonic frequency, thereby providing both impedance matching at said fundamental frequency and harmonic rejection of at least two different harmonics of said fundamental frequency by said first shunt arm;

a series arm comprising a third inductor and a third capacitor in parallel, having a first, impedance-matching-required inductance at said fundamental frequency, and wherein said third capacitor acts as an open circuit at said fundamental frequency and parallel resonates with said third inductor at a third harmonic frequency, thereby providing rejection of said third harmonic frequency; and

a second shunt arm located between said first inductive element and an output port of said circuit, said second shunt arm comprising a fourth capacitor and a fourth inductor in series, and having a second, impedance-matching-required capacitance at said fundamental frequency (F_o), and a series resonance in the vicinity of a fourth harmonic frequency, thereby providing both said second impedance matching required capacitance at said fundamental frequency (f_o) and harmonic rejection at said fourth harmonic frequency, wherein (i) said first shunt path provides harmonic rejection at said first harmonic frequency, (ii) said second shunt path provides harmonic rejection at said second harmonic frequency, and (iii) said first shunt path and said second shunt path in combination parallel resonate to an open circuit at a frequency substantially equal to said series resonance of said fourth capacitor and said fourth inductor in said second shunt arm.

5. The circuit recited in claim 4 wherein said third inductor and said fourth inductor are in physical proximity, thereby establishing a mutual inductance between said third and fourth inductor, said mutual inductance having a coefficient of mutual inductance of greater than 0.20.

6. The circuit recited in claim 4 wherein said impedance matching circuit is implemented as a monolithic integrated circuit.