Method and software for partitioned floating-point multiply-add operation

• US 7,660,972 B2
• Filed: 01/16/2004
• Issued: 02/09/2010
• Est. Priority Date: 08/16/1995
• Status: Expired due to Fees

• Current Assignee: Microunity Systems Engineering Incorporated
• Original Assignee: Microunity Systems Engineering Incorporated
• Inventors: Moussouris, John, Hansen, Craig
• Primary Examiner(s): Coleman; Eric
• Application Number:
  US10/757,851
• Publication Number:
  US 20040205324A1
• Time in Patent Office: 2,216 Days
• Field of Search: 712/222
• US Class Current: 712/222
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30029 Logical and Boolean instructions, e.g. XOR, NOT
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/3816 Instruction alignment, e.g. cache line crossing
• CPC Class Codes: G06F 9/3824 : Operand accessing
• CPC Class Codes: G06F 9/383 : Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3861 : Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3873 : Variable length pipelines, e.g. elastic pipeline
• CPC Class Codes: G06F 9/3885 : using a plurality of independent parallel functional units

Abstract

A method and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying three registers each containing a plurality of data elements, the execution unit operable to multiply the first and second registers and add the third register to produce a catenated result containing a plurality of data elements. Additional instructions provide group floating-point subtract, add, multiply, set less, and set greater equal operations. The set less and set greater equal operations produce alternatively zero or an identity element for each element of a catenated result, the result facilitating alternative selection of individual data elements using bitwise Boolean operations and without requiring conditional branch operations.

Claims

1. A method for processing data in a programmable processor, the method comprising:

decoding and executing instructions that instruct a computer system to perform operations,

at least some of the instructions including group floating-point instructions each operating on first and second registers partitioned into a plurality of floating point operands, the floating point operands having a defined precision and the defined precision being dynamically variable, having a defined result precision which is equal to the defined precision of the operands;

at least one group floating-point instruction being a group floating-point multiply-and-add instruction, further operating on a third register partitioned into a plurality of floating-point operands,

operable to multiply the plurality of floating-point operands in the first and second registers and add the plurality of floating-point operands in the third register, each producing a floating-point value to provide a plurality of floating-point values, each of the floating-point values capable of being represented by the defined result precision, and a catenated result having a plurality of partitioned fields for the plurality of floating point values.

2. The method of claim 1, wherein

at least one group floating-point instruction being a member of the collection consisting of group floating-point subtract, group floating-point add, and group floating-point multiply,

operable to perform a subtract, add or multiply respectively on the plurality of floating-point operands in the first and second registers, to provide a plurality of floating-point values, each of the floating-point values capable of being represented by the defined result precision, and a catenated result having a plurality of partitioned fields for the plurality of floating point values;

and

at least one group floating-point instruction being a member of the collection consisting of group floating-point set less, and group floating-point set greater or equal,

operable to perform a set-less or set-greater-or-equal operation, respectively, on the plurality of floating-point operands in the first and second registers, to provide a plurality of values, each of the values capable of being represented by the defined result precision, and a catenated result having a plurality of partitioned fields for the plurality of values, wherein the value is zero if the operation produces a false result, and wherein the value is an identity value if the operation produces a true result; and

at least some of the instructions comprising performing data manipulations on multiple operands stored in partitioned fields of registers wherein the data manipulations comprise copying or rearranging operands.

3. The method of claim 2 wherein the zero value and the identity value are values that construct a bit mask operable to select between alternate expressions using a bitwise Boolean operation.

4. The method of claim 1 wherein the catenated result has a width of 128 bits.

5. The method of claim 1 wherein the catenated result is provided to a register.

6. The method of claim 1 wherein the defined precision is 16 bits.

7. The method of claim 1 wherein the defined precision is a format comprising one sign bit, five exponent bits and ten significand bits.

8. The method of claim 1 wherein the defined precision is 32 bits.

9. The method of claim 1 wherein the precision of the group floating-point instructions is a format comprising one sign bit, eight exponent bits and 23 significand bits.

10. The method of claim 1 wherein the defined precision is 64 bits.

11. The method of claim 1 wherein the precision of the group floating-point instructions is a format comprising one sign bit, eleven exponent bits and 52 significand bits.

12. A computer-readable storage medium having stored therein a plurality of instructions that cause a computer processor to perform data operations:

at least some of the instructions including group floating-point instructions each operating on first and second registers partitioned into a plurality of floating point operands, the floating point operands having a defined precision and the defined precision being dynamically variable, having a defined result precision which is equal to the defined precision of the operands;

the group floating-point instructions including a group floating-point multiply-and-add instruction, further operating on a third register partitioned into a plurality of floating-point operands,

the group floating-point multiply-and-add instruction operable to multiply the plurality of floating-point operands in the first and second registers and add the plurality of floating-point operands in the third register, each producing a floating-point value to provide a plurality of floating-point values, each of the floating-point values capable of being represented by the defined result precision, and a catenated result having a plurality of partitioned fields for the plurality of floating point values.

13. The computer-readable storage medium of claim 12,

at least one group floating-point instruction being a member of the collection consisting of group floating-point subtract, group floating-point add, and group floating-point multiply,

operable to perform a subtract, add or multiply respectively on the plurality of floating-point operands in the first and second registers, to provide a plurality of floating-point values, each of the floating-point values capable of being represented by the defined result precision, and a catenated result having a plurality of partitioned fields for the plurality of floating point values;

and

at least one group floating-point instruction being a member of the collection consisting of group floating-point set less, and group floating-point set greater or equal,

operable to perform a set-less or set-greater-or-equal operation, respectively, on the plurality of floating-point operands in the first and second registers, to provide a plurality of values, each of the values capable of being represented by the defined result precision, and a catenated result having a plurality of partitioned fields for the plurality of values, wherein the value is zero if the operation produces a false result, and wherein the value is an identity value if the operation produces a true result; and

at least some of the instructions comprising performing data manipulations on multiple operands stored in partitioned fields of registers wherein the data manipulations comprise copying or rearranging operands.

14. The computer-readable storage medium of claim 13 wherein the zero value and the identity value are values that construct a bit mask operable to select between alternate expressions using a bitwise Boolean operation.

15. The computer-readable storage medium of claim 12 wherein the catenated result has a width of 128 bits.

16. The computer-readable storage medium of claim 12 wherein the catenated result is provided to a register.

17. The computer-readable storage medium of claim 12 wherein the defined precision is 16 bits.

18. The computer-readable storage medium of claim 12 wherein the defined precision is a format comprising one sign bit, five exponent bits and ten significand bits.

19. The computer-readable storage medium of claim 12 wherein the defined precision is 32 bits.

20. The computer-readable storage medium of claim 12 wherein the precision of the group floating-point instructions is a format comprising one sign bit, eight exponent bits and 23 significand bits.

21. The computer-readable storage medium of claim 12 wherein the defined precision is 64 bits.

22. The computer-readable storage medium of claim 12 wherein the precision of the group floating-point instructions is a format comprising one sign bit, eleven exponent bits and 52 significand bits.

23. A method for performing data operations in a programmable processor comprising:

executing a plurality of instructions each of which (i) operates on data stored in a first, a second and a third register, the data in the first register comprising a first plurality of equal-sized data elements, the data in the second register comprising a second plurality of equal-sized data elements, the data in the third register comprising a third plurality of equal-sized data elements, (ii) multiplies each data element in the first register with a corresponding data element in the second register to produce a plurality of products, and (iii) adds each product in the plurality of products to a corresponding data element in the third register to produce a plurality of sums, and (iv) provides the plurality of sums as a catenated result;

wherein the plurality of instructions includes a floating-point instruction that operates on floating-point data elements stored in the first, second and third registers.

24. The method of claim 23 wherein each of the plurality of instructions includes a field that indicates the size of each of the first plurality and second plurality of data elements.

25. The method of claim 23 wherein the catenated result is returned to a fourth register.

26. The method of claim 23 wherein for the floating-point instruction, each of the first plurality and second plurality of equal-sized data elements is a floating-point value that is n bits wide, and each of the third plurality of equal-sized data elements is also a floating-point value that is n bits wide.

27. The method of claim 26 wherein the floating-point instruction multiplies data elements of 32-bit floating-point data and adds data elements of 32-bit floating-point data.

28. The method of claim 23 wherein the plurality of instructions includes an integer instruction that operates on integer data elements stored in the first, second and third registers.

29. The method of claim 28 wherein for the integer instruction, each of the first plurality and second plurality of equal-sized data elements is an integer value that is n bits wide, and each of the third plurality of equal-sized data elements is an integer value that is 2※

n bits wide.

30. The method of claim 29 wherein the integer instruction multiplies data elements of 8-bit integer data and adds data elements of 16-bit integer data.

31. The method of claim 29 wherein the integer instruction multiplies data elements of 16-bit integer data and adds data elements of 32-bit integer data.

32. The method of claim 29 wherein the integer instruction multiplies data elements of 32-bit integer data and adds data elements of 64-bit integer data.

33. A computer-readable storage medium having stored therein instructions that cause a computer processor to perform operations on data stored in registers in the computer processor, the instructions comprising:

a plurality of instructions each of which (i) operates on data stored in a first, a second and a third register, the data in the first register comprising a first plurality of equal-sized data elements, the data in the second register comprising a second plurality of equal-sized data elements, the data in the third register comprising a third plurality of equal-sized data elements, (ii) multiplies each data element in the first register with a corresponding data element in the second register to produce a plurality of products, and (iii) adds each product in the plurality of products to a corresponding data element in the third register to produce a plurality of sums, and (iv) provides the plurality of sums as a catenated result;

wherein the plurality of instructions includes a floating-point instruction that operates on floating-point data elements stored in the first, second and third registers.

34. The computer-readable storage medium of claim 33 wherein each of the plurality of instructions includes a field that indicates the size of each of the first plurality and second plurality of data elements.

35. The computer-readable storage medium of claim 33 wherein the catenated result is returned to a fourth register.

36. The computer-readable storage medium of claim 33 wherein for the floating-point instruction, each of the first plurality and second plurality of equal-sized data elements is a floating-point value that is n bits wide, and each of the third plurality of equal-sized data elements is also a floating-point value that is n bits wide.

37. The computer-readable storage medium of claim 36 wherein the floating-point instruction multiplies data elements of 32-bit floating-point data and adds data elements of 32-bit floating-point data.

38. The computer-readable storage medium of claim 33 wherein the plurality of instructions includes an integer instruction that operates on integer data elements stored in the first, second and third registers.

39. The computer-readable storage medium of claim 38 wherein for the integer instruction, each of the first plurality and second plurality of equal-sized data elements is an integer value that is n bits wide, and each of the third plurality of equal-sized data elements is an integer value that is 2※

n bits wide.

40. The computer-readable storage medium of claim 39 wherein the integer instruction multiplies data elements of 8-bit integer data and adds data elements of 16-bit integer data.

41. The computer-readable storage medium of claim 39 wherein the integer instruction multiplies data elements of 16-bit integer data and adds data elements of 32-bit integer data.

42. The computer-readable storage medium of claim 39 wherein the integer instruction multiplies data elements of 32-bit integer data and adds data elements of 64-bit integer data.