System and apparatus for group data operations
DCFirst Claim
1. A programmable processor comprising:
- (a) an instruction path and a data path;
(b) an external interface operable to receive data from an external source and communicate the received data over the data path;
(c) a register file comprising a plurality of registers coupled to the data path; and
(d) an execution unit, coupled to the instruction and data paths, that is operable to decode and execute instructions received from the instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results,wherein the execution unit is capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions, the group data handling instructions comprising a plurality of swap instructions, each swap instruction operating on segments of data in an operand register, each segment consisting of a plurality of data elements, the size of the segments and the size of the data elements being variable from one swap instruction to another and specified by the instruction, each swap instruction reversing the order of the plurality of data elements within each segment within the operand register, to produce a catenated result returned to a register in the register file.
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Abstract
Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on multiple data elements stored registers in a register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results, wherein the execution unit is capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions.
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Citations
22 Claims
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1. A programmable processor comprising:
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(a) an instruction path and a data path; (b) an external interface operable to receive data from an external source and communicate the received data over the data path; (c) a register file comprising a plurality of registers coupled to the data path; and (d) an execution unit, coupled to the instruction and data paths, that is operable to decode and execute instructions received from the instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results, wherein the execution unit is capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions, the group data handling instructions comprising a plurality of swap instructions, each swap instruction operating on segments of data in an operand register, each segment consisting of a plurality of data elements, the size of the segments and the size of the data elements being variable from one swap instruction to another and specified by the instruction, each swap instruction reversing the order of the plurality of data elements within each segment within the operand register, to produce a catenated result returned to a register in the register file. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11)
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2. The programmable processor of claim wherein the plurality of swap instructions comprises first, second, third, fourth, fifth, and sixth swap instructions,
wherein for the first swap instruction, the data elements are each 8 bits wide, and the segments are each 16 bits wide, wherein for the second swap instruction, the data elements are each 8 bits wide, and the segments are each 32 bits wide, wherein for the third swap instruction, the data elements are each 16 bits wide, and the segments are each 32 bits wide, wherein for the fourth swap instruction, the data elements are each 8 bits wide, and the segments are each 64 bits wide, wherein for the fifth swap instruction, the data elements are each 16 bits wide, and the segments are each 64 bits wide, and wherein for the sixth swap instruction, the data elements are each 32 bits wide, and the segments are each 64 bits wide.
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12. A data processing system comprising:
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a bus coupling components in the data processing system; an external memory coupled to the bus; and a programmable processor coupled to the bus, the processor comprising (a) an instruction path and a data path, (b) an external interface operable to receive data from an external source and communicate the received data over the data path, (c) a register file comprising a plurality of registers coupled to the data path, and (d) an execution unit, coupled to the instruction and data paths, that is operable to decode and execute instructions received from the instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results, wherein the execution unit is capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions, the group data handling instructions comprising a plurality of swap instructions, each swap instruction operating on segments of data in an operand register, each segment consisting of a plurality of data elements, the size of the segments and the size of the data elements being variable from one swap instruction to another and specified by the instruction, each swap instruction reversing the order of the plurality of data elements within each segment within the operand register, to produce a catenated result returned to a register in the register file. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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Specification