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Bus terminator/monitor/bridge systems and methods

  • US 7,661,024 B2
  • Filed: 10/31/2007
  • Issued: 02/09/2010
  • Est. Priority Date: 10/31/2007
  • Status: Expired due to Fees
First Claim
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1. A computing system, comprising:

  • a first bus;

    a second bus;

    a first processor coupled to and configured to control the first bus;

    a second processor coupled to and configured to control the second bus;

    a first plurality of devices in communication with the first processor via the first bus;

    a second plurality of devices in communication with the second processor via the second bus; and

    a terminator-monitor-bridge (TMB) device coupled between the first bus and the second bus, wherein the TMB device is configured to;

    selectively enable the first processor and the second processor to control at least a portion of the second bus and the first bus, respectively,enable the first processor to control a first portion of the second plurality of devices and enable the second processor to retain control of a second portion of the second plurality of devices if a fault is detected on the second bus between the first and second portions of the second plurality of devices, andenable the second processor to control a first portion of the first plurality of devices and enable the first processor to retain control of a second portion of the first plurality of devices if a fault is detected on the first bus between the first and second portions of the first plurality of devices.

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