Bus terminator/monitor/bridge systems and methods

• US 7,661,024 B2
• Filed: 10/31/2007
• Issued: 02/09/2010
• Est. Priority Date: 10/31/2007
• Status: Expired due to Fees

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Becker, Karl H., Dodgen, David R., DuBoise, Mark D.
• Primary Examiner(s): Cleary; Thomas J
• Assistant Examiner(s): VU, TRISHA U
• Application Number:
  US11/932,467
• Publication Number:
  US 20090113108A1
• Time in Patent Office: 832 Days
• Field of Search: None
• US Class Current: 714/11
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

Computing systems including first and second processors configured to control first and second buses, respectively, and a terminator-monitor-bridge (TMB) device coupled between the first and second buses are provided. The TMB device is configured to selectively enable the first processor and the second processor to control at least a portion of the second bus and the first bus, respectively. TMB devices and methods for operating the TMB devices in accordance with the above configuration are also provided.

Claims

1. A computing system, comprising:

a first bus;

a second bus;

a first processor coupled to and configured to control the first bus;

a second processor coupled to and configured to control the second bus;

a first plurality of devices in communication with the first processor via the first bus;

a second plurality of devices in communication with the second processor via the second bus; and

a terminator-monitor-bridge (TMB) device coupled between the first bus and the second bus, wherein the TMB device is configured to;

selectively enable the first processor and the second processor to control at least a portion of the second bus and the first bus, respectively,

enable the first processor to control a first portion of the second plurality of devices and enable the second processor to retain control of a second portion of the second plurality of devices if a fault is detected on the second bus between the first and second portions of the second plurality of devices, and

enable the second processor to control a first portion of the first plurality of devices and enable the first processor to retain control of a second portion of the first plurality of devices if a fault is detected on the first bus between the first and second portions of the first plurality of devices.

2. The computing system of claim 1, wherein the TMB is configured to:

temporarily enable the first processor to control the first portion of the second plurality of devices if the fault is detected on the second bus; and

temporarily enable the second processor to control the first portion of the first plurality of devices if the fault is detected on the first bus.

3. The computing system of claim 2, wherein the TMB is further configured to:

temporarily disable the first processor from controlling the second portion of the first plurality of devices if the fault is detected on the first bus; and

temporarily disable the second processor from controlling the second portion of the second plurality of devices if the fault is detected on the second bus.

4. The computing system of claim 3, wherein the TMB is further configured to:

enable the first processor to re-control the first portion of the first plurality of devices if the fault on the first bus is a first non-processor fault; and

enable the second processor to re-control the first portion of the second plurality of devices if the fault on the second bus is a second non-processor fault.

5. The computing system of claim 1, further comprising:

a first computing device including the first processor; and

a second computing device including the second processor.

6. The computing system of claim 1, wherein the first bus is a universal bus (USB) and the second bus is a USB.

7. The computing system of claim 1, wherein the first bus is an IEEE 1394 bus and the second bus is an IEEE 1394 bus.

8. The computing system of claim 1, wherein the first bus is an RS 422 bus and the second bus is an RS 422 bus.

9. The computing system of claim 1, wherein the first bus is an Ethernet bus and the second bus is an Ethernet bus.

10. A method for operating a terminator-monitor-bridge (TMB) device coupled between a first bus including a first plurality of devices controlled by a first processor and a second bus including a second plurality of devices controlled by a second processor, the method comprising the steps of:

monitoring the first bus and the second bus for faults;

at least temporarily enabling the first processor to control a first portion of the second plurality of devices and enabling the second processor to retain control of a second portion of the second plurality of devices if a fault is detected on the second bus between the first and second portions of the second plurality of devices; and

at least temporarily enabling the second processor to control a first portion of the first plurality of device and enabling the first processor to retain control of a second portion of the first plurality of devices if a fault is detected on the first bus between the first and second portions of the first plurality of devices.

11. The method of claim 10, further comprising the steps of:

enabling, on a non-temporary basis, the first processor to control the first portion of the second plurality of devices; and

enabling, on a non-temporary basis, the second processor to control the first portion of the first plurality of devices.

12. The method of claim 10, further comprising the steps of:

at least temporarily disabling the first processor from controlling the first portion of the first plurality of devices if the fault on the first bus is detected; and

at least temporarily disabling the second processor from controlling the first portion of the second plurality of devices if the fault on the second bus is detected.

13. The method of claim 12, further comprising the steps of:

enabling the first processor to re-control the first portion of the first plurality of devices if the fault on the first bus is a first non-processor fault; and

enabling the second processor to re-control the first portion of the second plurality of devices if the fault on the second bus is a second non-processor fault.

14. The method of claim 10, further comprising the steps of:

reporting bus status information including the fault for the second bus on the first bus; and

reporting bus status information including the fault for the first bus on the second bus.

15. The method of claim 10, wherein the step of at least temporarily enabling the first processor to control the first portion of the second plurality of devices comprises the step of enabling the first processor to control the first portion of the second plurality of devices independent of input other than the fault detected on the second bus;

and

wherein the step of at least temporarily enabling the second processor to control the first portion of the first plurality of devices comprises the step of enabling the second processor to control the first portion of the first plurality of devices independent of input other than the fault detected on the first bus.

16. A terminator-monitor-bridge (TMB) device configured to be coupled to a first bus including a first plurality of devices controlled by a first processor and a second bus including a second plurality of devices controlled by a second processor, the TMB device comprising:

means for monitoring the first bus and the second bus for faults;

means for at least temporarily enabling the first processor to control a first portion of the second plurality of devices and enabling the second processor to retain control of a second portion of the second plurality of devices if a fault is detected on the second bus between the first and second portions of the second plurality of devices; and

means for at least temporarily enabling the second processor to control a first portion of the first plurality of devices and enabling the first processor to retain control of a second portion of the first plurality of devices if a fault is detected on the first bus between the first and second portions of the first plurality of devices.

17. The TMB device of claim 16, further comprising:

means for enabling, on a non-temporary basis, the first processor to control the first portion of the second plurality of devices; and

means for enabling, on a non-temporary basis, the second processor to control the first portion of the first plurality of devices.

18. The TMB device of claim 16, further comprising:

means for at least temporarily disabling the first processor from controlling the first portion of the first plurality of devices if the fault on the first bus is detected; and

means for at least temporarily disabling the second processor from controlling the first portion of the second plurality of devices if the fault on the second bus is detected.

19. The TMB device of claim 18, further comprising:

means for enabling the first processor to re-control the first portion of the first plurality of devices if the fault on the first bus is a first non-processor fault; and

means for enabling the second processor to re-control the first portion of the second plurality of devices if the fault on the second bus is a second non-processor fault.