Manufacturing method of semiconductor device

• US 7,662,670 B2
• Filed: 07/19/2006
• Issued: 02/16/2010
• Est. Priority Date: 10/30/2002
• Status: Expired due to Fees

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Kuhara, Koichi, Yamada, Hiroshi, Suzuki, Akira, Noma, Takashi, Seki, Yoshinori, Shinogi, Hiroyuki, Takao, Yukihiro
• Primary Examiner(s): PHAM, THANHHA S
• Application Number:
  US11/488,890
• Publication Number:
  US 20070026639A1
• Time in Patent Office: 1,308 Days
• Field of Search: 438/110, 438112-114, 438/33, 438/68, 438/458, 438/460, 438/465, 257/E21.523
• US Class Current: 438/114
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68377 with parts of the auxiliary support remaining in the finished device
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3185 the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]

Abstract

A glass substrate is bonded through a resin to the top surface of a semiconductor wafer on which a first wiring is formed. A V-shaped groove is formed by notching from the back surface of the wafer. A second wiring connected with the first wiring and extending over the back surface of the wafer is formed. A protection film composed of an organic resin or a photoresist layer to provide protection with an opening is formed on the second wiring by spray coating. A conductive terminal is formed by screen printing using the protection film as a solder mask. A cushioning material may be formed on the back surface of the wafer by spray coating.

Claims

1. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor wafer comprising a first wiring formed on a front surface thereof;

bonding a supporting substrate to the front surface of the semiconductor wafer;

etching the semiconductor wafer to expose a portion of the first wiring;

forming a second wiring connected with the exposed portion of the first wiring and extending over a back surface of the semiconductor wafer; and

forming a protection film on the second wiring by spray coating.

2. The method of claim 1, further comprising forming an opening in the protection film at a predetermined position to expose the second wiring.

3. The method of claim 2, further comprising forming a conductive terminal on the second wiring through the opening in the protection film.

4. The method of claim 1, wherein the protection film comprises an organic resin.

5. The method of claim 4, wherein the organic resin comprises a photoresist resin or an epoxy resin.

6. The method of claim 1, wherein the etching of the semiconductor wafer comprises forming a groove having a shape of a line along a dicing line.

7. The method of claim 1, wherein the etching of the semiconductor wafer comprises forming pits that are discrete along a dicing line.

8. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor wafer comprising a first insulation film formed on a front surface thereof and a first wiring formed on the first insulation film;

bonding a supporting substrate to the front surface of the semiconductor wafer;

etching the semiconductor wafer to expose a portion of the first insulation film;

forming a second insulation film to cover a back surface of the semiconductor wafer and the exposed portion of the first insulation film;

etching the first and second insulation films to expose a portion of the first wiring;

forming a second wiring connected with the exposed portion of the first wiring and extending over the second insulation film; and

forming a protection film on the second wiring by spray coating.

9. The method of claim 8, further comprising forming an opening in the protection film at a predetermined position to expose the second wiring.

10. The method of claim 9, further comprising forming a conductive terminal on the second wiring through the opening in the protection film.

11. The method of claim 8, wherein the protection film comprises an organic resin.

12. The method of claim 11, wherein the organic resin comprises a photoresist resin or an epoxy resin.

13. The method of claim 8, wherein the etching of the semiconductor wafer comprises forming a groove having a shape of a line along a dicing line.

14. The method of claim 8, wherein the etching of the semiconductor wafer comprises forming pits that are discrete along a dicing line.

15. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor wafer comprising a first wiring formed on a front surface thereof;

bonding a supporting substrate to the front surface of the semiconductor wafer;

etching the semiconductor wafer to expose a portion of the first wiring;

forming a second wiring connected with the exposed portion of the first wiring and extending over a back surface of the semiconductor wafer;

forming a first protection film on the second wiring by spin coating; and

forming a second protection film on the second wiring by spray coating.

16. The method of claim 15, further comprising forming an opening in the first and second protection films at a predetermined position to expose a portion of the second wiring.

17. The method of claim 15, further comprising forming a terminal on the exposed portion of the second wiring.

18. The method of claim 15, wherein the first protection film is formed prior to the formation of the second protection film.

19. The method of claim 15, wherein the second protection film is formed prior to the formation of the first protection film.

20. The method of claim 15, wherein the etching of the semiconductor wafer comprises forming a groove having a shape of a line along a dicing line.

21. The method of claim 15, wherein the etching of the semiconductor wafer comprises forming pits that are discrete along a dicing line.