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Air gap under on-chip passive device

  • US 7,662,722 B2
  • Filed: 01/24/2007
  • Issued: 02/16/2010
  • Est. Priority Date: 01/24/2007
  • Status: Active Grant
First Claim
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1. A method of fabricating a microelectronic chip, comprising:

  • forming a plurality of front-end-of-line (“

    FEOL”

    ) devices in a semiconductor region of the microelectronic chip;

    forming a plurality of stacked interlevel dielectric (“

    ILD”

    ) layers overlying the plurality of FEOL devices, the plurality of stacked ILD layers including a first ILD layer and a second ILD layer overlying the first ILD layer, the second ILD layer being resistant to attack by a first etchant which attacks the first ILD layer;

    forming a passive device overlying at least the first ILD layer; and

    using the first etchant, removing a portion of the first ILD layer in registration with the passive device to form an air gap underlying and in registration with the passive device by a process including exposing a surface of the first ILD layer by etching openings in the second ILD layer and applying the first etchant to the first ILD layer through the openings.

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