Air gap under on-chip passive device

• US 7,662,722 B2
• Filed: 01/24/2007
• Issued: 02/16/2010
• Est. Priority Date: 01/24/2007
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Dalton, Timothy J., Murphy, William J., Chinthakindi, Anil K., Eshun, Ebenezer E., Gambino, Jeffrey P., Coolbaugh, Douglas D., Edelstein, Daniel C., Stamper, Anthony K., Vaed, Kunal
• Primary Examiner(s): CHEN, KIN CHAN
• Application Number:
  US11/626,548
• Publication Number:
  US 20080173976A1
• Time in Patent Office: 1,119 Days
• Field of Search: 438/700, 438/702, 438/706, 438/714, 438/719, 438/723, 438/724, 438/725
• US Class Current: 438/719
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method is provided for fabricating a microelectronic chip which includes a passive device such, as an inductor, overlying an air gap. In such method, a plurality of front-end-of-line (“FEOL”) devices are formed in a semiconductor region of the microelectronic chip, and a plurality of stacked interlevel dielectric (“ILD”) layers are formed to overlie the plurality of FEOL devices, the plurality of stacked ILD layers including a first ILD layer and a second ILD layer, where the second ILD layer is resistant to attack by a first etchant which attacks the first ILD layer. A passive device is formed to overlie at least the first ILD layer. Using the first etchant, a portion of the first ILD layer in registration with the passive device is removed to form an air gap which underlies the passive device in registration with the passive device.

Claims

1. A method of fabricating a microelectronic chip, comprising:

forming a plurality of front-end-of-line (“

FEOL”

) devices in a semiconductor region of the microelectronic chip;

forming a plurality of stacked interlevel dielectric (“

ILD”

) layers overlying the plurality of FEOL devices, the plurality of stacked ILD layers including a first ILD layer and a second ILD layer overlying the first ILD layer, the second ILD layer being resistant to attack by a first etchant which attacks the first ILD layer;

forming a passive device overlying at least the first ILD layer; and

using the first etchant, removing a portion of the first ILD layer in registration with the passive device to form an air gap underlying and in registration with the passive device by a process including exposing a surface of the first ILD layer by etching openings in the second ILD layer and applying the first etchant to the first ILD layer through the openings.

2. The method as claimed in claim 1, wherein the second ILD layer underlies the passive device and at least a portion of the second ILD layer remains after removing the portion of the first ILD layer, the remaining portion of the second ILD layer supporting the passive device.

3. The method as claimed in claim 1, wherein the first ILD layer consists essentially of an organic dielectric material and the second ILD layer consists essentially of an inorganic dielectric material which is resistant to attack by the first etchant.

4. The method as claimed in claim 1, wherein the second ILD layer has a major surface, each of the openings in the second ILD layer has a width in a direction aligned with a plane defined by the major surface and a length in another direction aligned with the plane, wherein neither one of the width nor the length is greater than about twice the other one of the width and the length.

5. The method as claimed in claim 1, wherein the second ILD layer has a major surface, each of the openings in the second ILD layer is elongated, each opening having a length in a direction of extension aligned with a plane defined by the major surface and a width in a direction across the opening.

6. The method as claimed in claim 1, wherein the passive device includes at least one of an inductor or a capacitor, wherein the step of forming the passive device includes forming a metal pattern included in the passive device while simultaneously forming a metal interconnect wiring pattern for interconnection with at least one of the plurality of FEOL devices.

7. The method as claimed in claim 1, further comprising sealing the openings in the second ILD layer after removing the portion of the first ILD layer.

8. The method as claimed in claim 1, further comprising depositing a material resistant to attack by the first etchant onto walls of the openings prior to the step of using the first etchant to remove the portion of the first ILD layer, the material protecting the walls during the removal of the portion.

9. The method as claimed in claim 1, wherein each of the plurality of conductors includes lateral edges, and the lateral edges of adjacent ones of the plurality of conductors are exposed within the openings.

10. A method of fabricating a microelectronic chip, comprising:

forming a plurality of front-end-of-line (“

FEOL”

) devices in a semiconductor region of the microelectronic chip;

forming an interlevel dielectric region (“

ILD”

) overlying the plurality of FEOL devices, the ILD being resistant to attack by a first etchant which attacks the semiconductor region;

forming a passive device overlying the ILD region; and

using the first etchant, removing a portion of the semiconductor region directly underlying the passive device to form an air gap underlying the passive device.

11. The method as claimed in claim 10, wherein the step of removing the portion of the semiconductor region includes exposing a surface of the semiconductor region by etching openings in the ILD region and supplying the first etchant through the etched openings to the exposed surface to remove the portion of the semiconductor region.

12. A method of fabricating a microelectronic chip, comprising:

forming a plurality of front-end-of-line (“

FEOL”

) devices in a semiconductor region of the microelectronic chip;

forming a plurality of stacked interlevel dielectric regions (“

ILDs”

) overlying the plurality of FEOL devices, the plurality of stacked ILDs including a first ILD layer and a second ILD layer, the second ILD layer being etch-resistant to a first etchant which attacks the first ILD layer;

using the first etchant, removing a portion of the first ILD layer to provide an air gap underlying the second ILD layer; and

then forming a passive device overlying the plurality of stacked ILDs, such that the air gap directly underlies the passive device.

13. The method as claimed in claim 12, further comprising forming a hard mask overlying the first ILD layer and forming openings in the hard mask prior to using the first etchant to remove the portion of the first ILD layer.

14. The method as claimed in claim 13, wherein the hard mask and the second ILD layer each includes an inorganic material and the first ILD layer includes a low dielectric constant organic dielectric material.

15. The method as claimed in claim 12, further comprising depositing a dielectric material to close the openings in the hard mask prior to forming the passive device.

16. The method as claimed in claim 12, wherein the first ILD layer includes an organic material, the second ILD layer includes an inorganic material which resists attack by a process which attacks the first ILD layer, and the second ILD layer overlies the first ILD layer.

17. The method as claimed in claim 16, further comprising exposing a surface of the first ILD layer by etching openings in the second ILD layer and the portion of the first ILD layer is removed by exposing the first ILD layer to something.