III-nitride light emitting device with reduced strain light emitting layer

• US 7,663,148 B2
• Filed: 12/22/2006
• Issued: 02/16/2010
• Est. Priority Date: 12/22/2006
• Status: Active Grant

• Current Assignee: Lumileds LLC (Apollo Global Management, Inc.)
• Original Assignee: Philips Lumileds Lighting Company LLC (Apollo Global Management, Inc.)
• Inventors: Krames, Michael R., Gardner, Nathan F., Romano, Linda T., David, Aurelien J. F., Yi, Sungsoo
• Primary Examiner(s): Williams; Alexander O
• Application Number:
  US11/615,479
• Publication Number:
  US 20080149942A1
• Time in Patent Office: 1,152 Days
• Field of Search: 257/12, 257/13, 257/79, 257/101, 257/89, 257/E33.043, 257/E33.074, 257/E33.025
• US Class Current: 257/79
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers

Abstract

In accordance with embodiments of the invention, strain is reduced in the light emitting layer of a III-nitride device by including a strain-relieved layer in the device. The surface on which the strain-relieved layer is grown is configured such that strain-relieved layer can expand laterally and at least partially relax. In some embodiments of the invention, the strain-relieved layer is grown over a textured semiconductor layer or a mask layer. In some embodiments of the invention, the strain-relieved layer is group of posts of semiconductor material.

Claims

1. A device comprising:

a mask layer having a plurality of openings;

a Ill-nitride structure comprising;

a plurality of posts of semiconductor material corresponding to the openings in the mask layer, wherein the plurality of posts are separated by an insulating material, and wherein in a plane parallel to a surface of the mask layer, a lateral extent of a cross section of the plurality of posts is at least 90% of a lateral extent of the device;

a light emitting layer disposed between an n-type region and a p-type region, wherein a major surface of the light emitting layer is substantially parallel to a surface of the mask layer.

2. The device of claim 1 wherein the mask layer comprises silicon and nitrogen.

3. The device of claim 1 wherein each of the posts has a diameter less than 150 nm.

4. The device of claim 1 wherein the light emitting layer is disposed within the posts.

5. The device of claim 1 further comprising a planar layer of p-type semiconductor material disposed over the plurality of posts.

6. The device of claim 1 further comprising a planar layer of n-type semiconductor material disposed over the plurality of posts.

7. The device of claim 1 wherein the posts have a height between 50 nm and 3 μ

m.

8. The device of claim 1 wherein the insulating material is one of air, a resistive III-nitride material, and an oxide of silicon.

9. The device of claim 1 wherein the posts are truncated polyhedrons.

10. The device of claim 1 wherein the posts are polyhedrons.

11. The device of claim 1 wherein the light emitting layer is a conformal layer formed over the posts.

12. The device of claim 1 wherein:

the light emitting layer has bulk lattice constant a_bulk corresponding to a lattice constant of a free standing material of a same composition as the light emitting layer;

the light emitting layer has an in-plane lattice constant a_in-plane corresponding to a lattice constant of the light emitting layer as grown in the structure; and

(a_in-plane−

a_bulk)/ a_bulk is less than 1%.

13. The device of claim 1 wherein the light emitting layer has a thickness greater than 50 angstroms.

14. The device of claim 1 wherein the light emitting layer is doped with silicon to a dopant concentration between 1×

10¹⁸ cm<sup>−

3</sup> and 1×

10²⁰ cm<sup>−

3</sup>.

15. The device of claim 1 further comprising:

contacts electrically connected to the n-type region and the p-type region; and

a cover disposed over the III-nitride semiconductor structure.