Vertical field-effect transistor and method of forming the same

• US 7,663,183 B2
• Filed: 06/19/2007
• Issued: 02/16/2010
• Est. Priority Date: 06/21/2006
• Status: Active Grant

• Current Assignee: Flextronics International USA Incorporated (Flex, Ltd.)
• Original Assignee: Flextronics International USA Incorporated (Flex, Ltd.)
• Inventors: Ha, Wonill, Brar, Berinder P. S.
• Primary Examiner(s): Pham; Thanh V
• Assistant Examiner(s): NGUYEN, DUY T V
• Application Number:
  US11/765,323
• Publication Number:
  US 20070298564A1
• Time in Patent Office: 973 Days
• Field of Search: 257135-137, 257/213, 257/328, 257/329, 257/330, 257/242, 257/155, 257/288, 257/327, 257/E29.262, 257/E29.257, 438/212, 438/137, 438/197, 438/156
• US Class Current: 257/328
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/872 Schottky diodes

Abstract

A semiconductor device, a method of forming the same, and a power converter including the semiconductor device. In one embodiment, the semiconductor device includes a heavily doped substrate, a source/drain contact below the heavily doped substrate, and a channel layer above the heavily doped substrate. The semiconductor device also includes a heavily doped source/drain layer above the channel layer and another source/drain contact above the heavily doped source/drain layer. The semiconductor device further includes pillar regions through the another source/drain contact, the heavily doped source/drain layer, and portions of the channel layer to form a vertical cell therebetween. Non-conductive regions of the semiconductor device are located in the portions of the channel layer within the pillar regions. The semiconductor device still further includes a gate above the non-conductive regions in the pillar regions. The semiconductor device may also include a Schottky diode including the channel layer and a Schottky contact.

Claims

1. A method of forming a semiconductor device, comprising:

forming a vertical field-effect transistor, including;

forming a heavily doped substrate,

forming a source/drain contact below said heavily doped substrate,

forming a channel layer above said heavily doped substrate,

forming a heavily doped source/drain layer above said channel layer,

forming another source/drain contact above said heavily doped source/drain layer,

patterning and etching a pillar region through said another source/drain contact, said heavily doped source/drain layer, and portions of said channel layer to form a vertical cell,

forming a non-conductive region in a portion of said channel layer within said pillar region, and

forming a gate above and beyond said non-conductive region in said pillar region in contact with said channel layer; and

forming a Schottky diode, including;

forming a Schottky contact on an exposed surface of said channel layer to provide an anode configured to cooperate with said channel layer to provide a cathode for said Schottky diode.

2. The method as recited in claim 1 wherein forming said vertical field-effect transistor further includes forming a heavily doped buffer layer on an upper surface of said heavily doped substrate before forming said channel layer.

3. The method as recited in claim 1 wherein said source/drain contact and said another source/drain contact are formed from an alloy including gold, germanium and nickel and said gate is formed with platinum.

4. The method as recited in claim 1 wherein said heavily doped substrate is n-doped with silicon.

5. The method as recited in claim 1 wherein said channel layer is n-doped with silicon.

6. The method as recited in claim 1 wherein forming said vertical field-effect transistor further includes:

forming a conformal dielectric layer across an upper surface of said semiconductor device and selectively removing portions thereof to form sidewall spacers within said pillar region before forming said non-conductive region; and

performing a wet etch on exposed surfaces of said semiconductor device to form undercut regions under said sidewall spacers before forming said non-conductive region.

7. The method as recited in claim 1 wherein said heavily doped substrate forms a source, said source/drain contact forms a source contact, said heavily doped source/drain layer forms a drain and said another source/drain contact forms a drain contact of said vertical field-effect transistor.

8. The method as recited in claim 1 wherein said vertical field-effect transistor is a depletion mode device.

9. The method as recited in claim 1 wherein a doping density or a thickness of said channel layer is limited to form said vertical field-effect transistor as an enhancement mode device.

10. The method as recited in claim 1 wherein said Schottky contact is formed with platinum.

11. A semiconductor device, comprising:

a vertical field-effect transistor, including;

a heavily doped substrate,

a source/drain contact below said heavily doped substrate,

a channel layer above said heavily doped substrate,

a heavily doped source/drain layer above said channel layer,

another source/drain contact above said heavily doped source/drain layer,

a pillar region through said another source/drain contact, said heavily doped source/drain layer, and portions of said channel layer to form a vertical cell therebetween,

a non-conductive region in a portion of said channel layer within said pillar region, and

a gate above and beyond said non-conductive region in said pillar region in contact with said channel layer; and

a Schottky diode, including;

a Schottky contact on an exposed surface of said channel layer to provide an anode configured to cooperate with said channel layer to provide a cathode for said Schottky diode.

12. The semiconductor device as recited in claim 11 wherein said vertical field-effect transistor further includes a heavily doped buffer layer between said heavily doped substrate and said channel layer.

13. The semiconductor device as recited in claim 11 wherein said source/drain contact and said another source/drain contact are formed from an alloy including gold, germanium and nickel and said gate is formed with platinum.

14. The semiconductor device as recited in claim 11 wherein said heavily doped substrate is n-doped with silicon.

15. The semiconductor device as recited in claim 11 wherein said channel layer is n-doped with silicon.

16. The semiconductor device as recited in claim 11 wherein said vertical field-effect transistor further includes sidewall spacers on opposing sides of said vertical cell within said pillar region, said gate being partially recessed in an undercut region under one of said sidewall spacers.

17. The semiconductor device as recited in claim 11 wherein said heavily doped substrate forms a source, said source/drain contact forms a source contact, said heavily doped source/drain layer forms a drain and said another source/drain contact forms a drain contact of said vertical field-effect transistor.

18. The semiconductor device as recited in claim 11 wherein said vertical field-effect transistor is a depletion mode device.

19. The semiconductor device as recited in claim 11 wherein a doping density or a thickness of said channel layer is limited to form said vertical field-effect transistor as an enhancement mode device.

20. The semiconductor device as recited in claim 11 wherein said Schottky contact is formed with platinum.

21. A power converter coupled to a source of electrical power and configured to provide a regulated output characteristic, comprising:

a semiconductor device, including;

a power switch formed as a vertical field-effect transistor, including;

a heavily doped substrate,

a source/drain contact below said heavily doped substrate,

a channel layer above said heavily doped substrate,

a heavily doped source/drain layer above said channel layer,

another source/drain contact above said heavily doped source/drain layer,

a pillar region through said another source/drain contact, said heavily doped source/drain layer, and portions of said channel layer to form a vertical cell therebetween,

a non-conductive region in a portion of said channel layer within said pillar region, and

a gate above and beyond said non-conductive region in said pillar region in contact with said channel layer, and

a Schottky diode, including;

a Schottky contact on an exposed surface of said channel layer to provide an anode configured to cooperate with said channel layer to provide a cathode for said Schottky diode;

a controller configured to control conduction intervals of said power switch to provide said regulated output characteristic; and

an output filter coupled to said power switch to filter said output characteristic.

22. The power converter as recited in claim 21 wherein said vertical field-effect transistor further includes a heavily doped buffer layer between said heavily doped substrate and said channel layer.

23. The power converter as recited in claim 21 wherein said source/drain contact and said another source/drain contact are formed from an alloy including gold, germanium and nickel and said gate is formed with platinum.

24. The power converter as recited in claim 21 wherein said heavily doped substrate is n-doped with silicon.

25. The power converter as recited in claim 21 wherein said channel layer is n-doped with silicon.

26. The power converter as recited in claim 21 wherein said vertical field-effect transistor further includes sidewall spacers on opposing sides of said vertical cell within said pillar region, said gate being partially recessed in an undercut region under one of said sidewall spacers.

27. The power converter as recited in claim 21 wherein said heavily doped substrate forms a source, said source/drain contact forms a source contact, said heavily doped source/drain layer forms a drain and said another source/drain contact forms a drain contact of said vertical field-effect transistor.

28. The power converter as recited in claim 21 wherein said vertical field-effect transistor is a depletion mode device.

29. The power converter as recited in claim 21 wherein a doping density or a thickness of said channel layer is limited to form said vertical field-effect transistor as an enhancement mode device.

30. The power converter as recited in claim 21 wherein said Schottky contact is formed with platinum.